mb/google/sarien: Add method to set GPIOs in romstage

Add method variant_romstage_gpio_table() with empty implementation to
be used in a subsequent commit for touchscreen power sequencing.
Call method in romstage to program any GPIOs that may need to be set.

TEST=tested with rest of patch train

Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Matt DeVillier 2023-02-23 19:18:45 -06:00
parent a358f2b4f7
commit 08da6eff8a
5 changed files with 21 additions and 0 deletions

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@ -3,6 +3,7 @@
#include <ec/google/wilco/romstage.h> #include <ec/google/wilco/romstage.h>
#include <soc/cnl_memcfg_init.h> #include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <variant/gpio.h>
static const struct cnl_mb_cfg memcfg = { static const struct cnl_mb_cfg memcfg = {
/* Access memory info through SMBUS. */ /* Access memory info through SMBUS. */
@ -44,7 +45,13 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd) void mainboard_memory_init_params(FSPM_UPD *memupd)
{ {
const struct pad_config *pads;
size_t pads_num;
wilco_ec_romstage_init(); wilco_ec_romstage_init();
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
pads = variant_romstage_gpio_table(&pads_num);
gpio_configure_pads(pads, pads_num);
} }

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@ -254,6 +254,12 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
return early_gpio_table; return early_gpio_table;
} }
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = 0;
return NULL;
}
static const struct cros_gpio cros_gpios[] = { static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),

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@ -14,5 +14,6 @@
const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num);
const struct pad_config *variant_romstage_gpio_table(size_t *num);
#endif #endif

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@ -242,6 +242,12 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
return early_gpio_table; return early_gpio_table;
} }
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = 0;
return NULL;
}
static const struct cros_gpio cros_gpios[] = { static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),

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@ -14,5 +14,6 @@
const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num);
const struct pad_config *variant_romstage_gpio_table(size_t *num);
#endif #endif