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ARMv7: De-uboot-ify Exynos5250 code 

When starting the Exynos5250 port, a lot of unneeded u-boot code
was imported. This is an attempt to get rid of a lot of unneeded
code before the port is used as a basis for further ARM ports.

There is a lot more that can be done, including cleaning up the
5250's Kconfig file.

Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3642
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Stefan Reinauer 2013-05-14 16:57:50 -07:00 committed by Stefan Reinauer
parent f73de9b975
commit 08dc357146
85 changed files with 718 additions and 3301 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/armv7/bootblock_simple.c
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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Google Inc
* Copyright 2010 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as

2
src/arch/armv7/include/arch/cache.h
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@ -32,6 +32,8 @@
#ifndef ARMV7_CACHE_H
#define ARMV7_CACHE_H
#include <stdint.h>
/* SCTLR bits */
#define SCTLR_M (1 << 0) /* MMU enable */
#define SCTLR_A (1 << 1) /* Alignment check enable */

2
src/arch/armv7/include/arch/cpu.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Google, Inc
* Copyright 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

98
src/arch/armv7/include/arch/gpio.h
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@ -1,98 +0,0 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* Copyright (c) 2011, NVIDIA Corp. All rights reserved.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_GENERIC_GPIO_H_
#define _ASM_GENERIC_GPIO_H_
/*
* Generic GPIO API for U-Boot
*
* GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
* by the SOC/architecture.
*
* Each GPIO can be an input or output. If an input then its value can
* be read as 0 or 1. If an output then its value can be set to 0 or 1.
* If you try to write an input then the value is undefined. If you try
* to read an output, barring something very unusual, you will get
* back the value of the output that you previously set.
*
* In some cases the operation may fail, for example if the GPIO number
* is out of range, or the GPIO is not available because its pin is
* being used by another function. In that case, functions may return
* an error value of -1.
*/
/**
* Stop using the GPIO. This function should not alter pin configuration.
*
* @param gpio GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_free(unsigned gpio);
/**
* Make a GPIO an input.
*
* @param gpio GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_direction_input(unsigned gpio);
/**
* Make a GPIO an output, and set its value.
*
* @param gpio GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_direction_output(unsigned gpio, int value);
/**
* Get a GPIO's value. This will work whether the GPIO is an input
* or an output.
*
* @param gpio GPIO number
* @return 0 if low, 1 if high, -1 on error
*/
int gpio_get_value(unsigned gpio);
/**
* Set an output GPIO's value. The GPIO must already be an output or
* this function may have no effect.
*
* @param gpio GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_set_value(unsigned gpio, int value);
/**
* Request ownership of a gpio. This should be called before any of the other
* functions are used on this gpio.
*
* @param gp GPIO number
* @param label User label for this GPIO
* @return 0 if ok, -1 on error
*/
int gpio_request(unsigned gpio, const char *label);
#endif /* _ASM_GENERIC_GPIO_H_ */

190
src/arch/armv7/include/arch/io.h
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@ -2,7 +2,7 @@
* Originally imported from linux/include/asm-arm/io.h. This file has changed
* substantially since then.
*
* Copyright (C) 2013 Google Inc.
* Copyright 2013 Google Inc.
* Copyright (C) 1996-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
@ -130,192 +130,4 @@ static inline void write32(uint32_t val, const void *addr)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
/*
* IO port access primitives
* -------------------------
*
* The ARM doesn't have special IO access instructions; all IO is memory
* mapped. Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* Note that for a big endian machine, this implies that the following
* big endian mode connectivity is in place, as described by numerous
* ARM documents:
*
* PCI: D0-D7 D8-D15 D16-D23 D24-D31
* ARM: D24-D31 D16-D23 D8-D15 D0-D7
*
* The machine specific io.h include defines __io to translate an "IO"
* address to a memory address.
*
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions.
*
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#ifdef __io
#define outb(v,p) writeb(v,__io(p))
#define outw(v,p) writew(cpu_to_le16(v),__io(p))
#define outl(v,p) writel(cpu_to_le32(v),__io(p))
#define inb(p) ({ unsigned int __v = readb(__io(p)); __v; })
#define inw(p) ({ unsigned int __v = le16_to_cpu(readw(__io(p))); __v; })
#define inl(p) ({ unsigned int __v = le32_to_cpu(readl(__io(p))); __v; })
#define outsb(p,d,l) writesb(__io(p),d,l)
#define outsw(p,d,l) writesw(__io(p),d,l)
#define outsl(p,d,l) writesl(__io(p),d,l)
#define insb(p,d,l) readsb(__io(p),d,l)
#define insw(p,d,l) readsw(__io(p),d,l)
#define insl(p,d,l) readsl(__io(p),d,l)
#endif
#define outb_p(val,port) outb((val),(port))
#define outw_p(val,port) outw((val),(port))
#define outl_p(val,port) outl((val),(port))
#define inb_p(port) inb((port))
#define inw_p(port) inw((port))
#define inl_p(port) inl((port))
#define outsb_p(port,from,len) outsb(port,from,len)
#define outsw_p(port,from,len) outsw(port,from,len)
#define outsl_p(port,from,len) outsl(port,from,len)
#define insb_p(port,to,len) insb(port,to,len)
#define insw_p(port,to,len) insw(port,to,len)
#define insl_p(port,to,len) insl(port,to,len)
/*
* ioremap and friends.
*
* ioremap takes a PCI memory address, as specified in
* linux/Documentation/IO-mapping.txt. If you want a
* physical address, use __ioremap instead.
*/
extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
extern void __iounmap(void *addr);
/*
* Generic ioremap support.
*
* Define:
* iomem_valid_addr(off,size)
* iomem_to_phys(off)
*/
#ifdef iomem_valid_addr
#define __arch_ioremap(off,sz,nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off),_size,nocache); \
_ret; \
})
#define __arch_iounmap __iounmap
#endif
/*
* String version of IO memory access ops:
*/
extern void _memcpy_fromio(void *, unsigned long, size_t);
extern void _memcpy_toio(unsigned long, const void *, size_t);
extern void _memset_io(unsigned long, int, size_t);
extern void __readwrite_bug(const char *fn);
/*
* If this architecture has PCI memory IO, then define the read/write
* macros. These should only be used with the cookie passed from
* ioremap.
*/
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = readb(__mem_pci(c)); __v; })
#define readw(c) ({ unsigned int __v = le16_to_cpu(readw(__mem_pci(c))); __v; })
#define readl(c) ({ unsigned int __v = le32_to_cpu(readl(__mem_pci(c))); __v; })
#define writeb(v,c) writeb(v,__mem_pci(c))
#define writew(v,c) writew(cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) writel(cpu_to_le32(v),__mem_pci(c))
#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
#define eth_io_copy_and_sum(s,c,l,b) \
eth_copy_and_sum((s),__mem_pci(c),(l),(b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#endif /* __mem_pci */
/*
* If this architecture has ISA IO, then define the isa_read/isa_write
* macros.
*/
#ifdef __mem_isa
#define isa_readb(addr) readb(__mem_isa(addr))
#define isa_readw(addr) readw(__mem_isa(addr))
#define isa_readl(addr) readl(__mem_isa(addr))
#define isa_writeb(val,addr) writeb(val,__mem_isa(addr))
#define isa_writew(val,addr) writew(val,__mem_isa(addr))
#define isa_writel(val,addr) writel(val,__mem_isa(addr))
#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c))
#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c))
#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c))
#define isa_eth_io_copy_and_sum(a,b,c,d) \
eth_copy_and_sum((a),__mem_isa(b),(c),(d))
static inline int
isa_check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (isa_readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#else /* __mem_isa */
#define isa_readb(addr) (__readwrite_bug("isa_readb"),0)
#define isa_readw(addr) (__readwrite_bug("isa_readw"),0)
#define isa_readl(addr) (__readwrite_bug("isa_readl"),0)
#define isa_writeb(val,addr) __readwrite_bug("isa_writeb")
#define isa_writew(val,addr) __readwrite_bug("isa_writew")
#define isa_writel(val,addr) __readwrite_bug("isa_writel")
#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io")
#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio")
#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio")
#define isa_eth_io_copy_and_sum(a,b,c,d) \
__readwrite_bug("isa_eth_io_copy_and_sum")
#define isa_check_signature(io,sig,len) (0)
#endif /* __mem_isa */
#endif /* __ASM_ARM_IO_H */

35
src/arch/armv7/include/arch/pci_ops.h
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@ -1,19 +1,28 @@
#ifndef ARCH_I386_PCI_OPS_H
#define ARCH_I386_PCI_OPS_H
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern const struct pci_bus_operations pci_cf8_conf1;
#if CONFIG_MMCONF_SUPPORT
extern const struct pci_bus_operations pci_ops_mmconf;
#endif
#ifndef ARCH_ARMV7_PCI_OPS_H
#define ARCH_ARMV7_PCI_OPS_H
static inline const struct pci_bus_operations *pci_config_default(void)
{
return &pci_cf8_conf1;
return NULL;
}
static inline void pci_set_method(device_t dev)
{
dev->ops->ops_pci_bus = pci_config_default();
}
#endif /* ARCH_I386_PCI_OPS_H */
#endif

432
src/arch/armv7/include/common.h
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@ -1,432 +0,0 @@
/*
* (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __COMMON_H_
#define __COMMON_H_ 1
#ifndef __ASSEMBLER__ /* put C only stuff in this section */
#include <types.h>
#ifdef DEBUG
#define debug(fmt,args...) printf (fmt ,##args)
#define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args);
#else
#define debug(fmt,args...)
#define debugX(level,fmt,args...)
#endif /* DEBUG */
#ifdef DEBUG
# define _DEBUG 1
#else
# define _DEBUG 0
#endif
/*
* An assertion is run-time check done in debug mode only. If DEBUG is not
* defined then it is skipped. If DEBUG is defined and the assertion fails,
* then it calls panic*( which may or may not reset/halt U-Boot (see
* CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
* before release, and after release it is hoped that they don't matter. But
* in any case these failing assertions cannot be fixed with a reset (which
* may just do the same assertion again).
*/
void __assert_fail(const char *assertion, const char *file, unsigned line,
const char *function);
#define assert(x) \
({ if (!(x) && _DEBUG) \
__assert_fail(#x, __FILE__, __LINE__, __func__); })
#define error(fmt, args...) do { \
printf("ERROR: " fmt "\nat %s:%d/%s()\n", \
##args, __FILE__, __LINE__, __func__); \
} while (0)
#ifndef BUG
#define BUG() do { \
printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
panic("BUG!"); \
} while (0)
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
#endif /* BUG */
/* Force a compilation error if condition is true */
#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
typedef void (interrupt_handler_t)(void *);
/*
* Return the time since boot in microseconds, This is needed for bootstage
* and should be defined in CPU- or board-specific code. If undefined then
* millisecond resolution will be used (the standard get_timer()).
*/
unsigned long timer_get_boot_us(void);
/*
* Return the current value of a monotonically increasing microsecond timer.
* Granularity may be larger than 1us if hardware does not support this.
*/
unsigned long timer_get_us(void);
/*
* General Purpose Utilities
*/
#if 0
#define min(X, Y) \
({ typeof (X) __x = (X); \
typeof (Y) __y = (Y); \
(__x < __y) ? __x : __y; })
#define max(X, Y) \
({ typeof (X) __x = (X); \
typeof (Y) __y = (Y); \
(__x > __y) ? __x : __y; })
#define MIN(x, y) min(x, y)
#define MAX(x, y) max(x, y)
#endif
/**
* container_of - cast a member of a structure out to the containing structure
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*
*/
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
/*
* Function Prototypes
*/
int init_timer(void); /* FIXME(dhendrix): used to be timer_init() */
int cpu_init(void);
/* */
unsigned long long initdram (int);
int display_options (void);
void print_size(unsigned long long, const char *);
int print_buffer (unsigned long addr, void* data, unsigned int width, unsigned int count, unsigned int linelen);
/* common/main.c */
void main_loop (void);
int run_command (const char *cmd, int flag);
int readline (const char *const prompt);
int readline_into_buffer (const char *const prompt, char * buffer);
int parse_line (char *, char *[]);
void init_cmd_timeout(void);
void reset_cmd_timeout(void);
/* arch/$(ARCH)/lib/board.c */
void board_init_f (void);
int checkboard (void);
int checkflash (void);
int checkdram (void);
int last_stage_init(void);
extern unsigned long monitor_flash_len;
int mac_read_from_eeprom(void);
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
# include <asm/setup.h>
# include <asm/u-boot-arm.h> /* ARM version to be fixed! */
#endif /* CONFIG_ARM */
int misc_init_f (void);
int misc_init_r (void);
/* common/exports.c */
void jumptable_init(void);
/* common/kallsysm.c */
const char *symbol_lookup(unsigned long addr, unsigned long *caddr);
/* api/api.c */
void api_init (void);
/* common/memsize.c */
long get_ram_size (long *, long);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
void fdc_hw_init (void);
/* $(BOARD)/eeprom.c */
void eeprom_init (void);
#ifndef CONFIG_SPI
int eeprom_probe (unsigned dev_addr, unsigned offset);
#endif
int eeprom_read (unsigned dev_addr, unsigned offset, unsigned char *buffer, unsigned cnt);
int eeprom_write (unsigned dev_addr, unsigned offset, unsigned char *buffer, unsigned cnt);
/*
* Set this up regardless of board
* type, to prevent errors.
*/
#if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR)
# define CONFIG_SYS_DEF_EEPROM_ADDR 0
#else
#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
#endif
#endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */
#if defined(CONFIG_SPI)
extern void spi_init_f (void);
extern void spi_init_r (void);
extern ssize_t spi_read (unsigned char *, int, unsigned char *, int);
extern ssize_t spi_write (unsigned char *, int, unsigned char *, int);
#endif
/* $(BOARD)/$(BOARD).c */
int board_early_init_f (void);
int board_late_init (void);
int board_postclk_init (void); /* after clocks/timebase, before env/serial */
int board_early_init_r (void);
void board_poweroff (void);
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram(void);
#endif /* CONFIG_SYS_DRAM_TEST */
/* $(CPU)/start.S */
#if defined(CONFIG_5xx) || \
defined(CONFIG_8xx)
unsigned int get_immr (unsigned int);
#endif
unsigned int get_pir (void);
#if defined(CONFIG_MPC5xxx)
unsigned int get_svr (void);
#endif
unsigned int get_pvr (void);
unsigned int get_svr (void);
unsigned int rd_ic_cst (void);
void wr_ic_cst (unsigned int);
void wr_ic_adr (unsigned int);
unsigned int rd_dc_cst (void);
void wr_dc_cst (unsigned int);
void wr_dc_adr (unsigned int);
int icache_status (void);
void icache_enable (unsigned long start, unsigned long size);
void icache_disable(void);
int dcache_status (void);
void dcache_enable (unsigned long start, unsigned long size);
void dcache_disable(void);
void mmu_disable(void);
unsigned long get_endaddr (void);
void trap_init (unsigned long);
#if defined (CONFIG_4xx) || \
defined (CONFIG_MPC5xxx) || \
defined (CONFIG_74xx_7xx) || \
defined (CONFIG_74x) || \
defined (CONFIG_75x) || \
defined (CONFIG_74xx) || \
defined (CONFIG_MPC8220) || \
defined (CONFIG_MPC85xx) || \
defined (CONFIG_MPC86xx) || \
defined (CONFIG_MPC83xx)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
unsigned short in16(unsigned int);
unsigned short in16r(unsigned int);
void out16(unsigned int, unsigned short value);
void out16r(unsigned int, unsigned short value);
unsigned long in32(unsigned int);
unsigned long in32r(unsigned int);
void out32(unsigned int, unsigned long value);
void out32r(unsigned int, unsigned long value);
void ppcDcbf(unsigned long value);
void ppcDcbi(unsigned long value);
void ppcSync(void);
void ppcDcbz(unsigned long value);
#endif
/* $(CPU)/cpu.c */
static inline int cpumask_next(int cpu, unsigned int mask)
{
for (cpu++; !((1 << cpu) & mask); cpu++)
;
return cpu;
}
#define for_each_cpu(iter, cpu, num_cpus, mask) \
for (iter = 0, cpu = cpumask_next(-1, mask); \
iter < num_cpus; \
iter++, cpu = cpumask_next(cpu, mask)) \
int cpu_numcores (void);
u32 cpu_mask (void);
int is_core_valid (unsigned int);
int probecpu (void);
int checkcpu (void);
int checkicache (void);
int checkdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int);
unsigned long get_tbclk (void);
/* $(CPU)/serial.c */
int serial_init (void);
void serial_setbrg (void);
void serial_putc (const char);
void serial_putc_raw(const char);
void serial_puts (const char *);
int serial_getc (void);
int serial_tstc (void);
void _serial_setbrg (const int);
void _serial_putc (const char, const int);
void _serial_putc_raw(const char, const int);
void _serial_puts (const char *, const int);
int _serial_getc (const int);
int _serial_tstc (const int);
/* $(CPU)/speed.c */
int get_clocks (void);
int get_clocks_866 (void);
int sdram_adjust_866 (void);
int adjust_sdram_tbs_8xx (void);
#if defined(CONFIG_8260)
int prt_8260_clks (void);
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
#if defined(CONFIG_MPC512X)
int prt_mpc512xxx_clks (void);
#endif
#if defined(CONFIG_MPC8220)
int prt_mpc8220_clks (void);
#endif
#ifdef CONFIG_4xx
unsigned long get_OPB_freq (void);
unsigned long get_PCI_freq (void);
#endif
#if defined(CONFIG_S3C24X0) || \
defined(CONFIG_LH7A40X) || \
defined(CONFIG_S3C6400) || \
defined(CONFIG_EP93XX)
unsigned long get_FCLK (void);
unsigned long get_HCLK (void);
unsigned long get_PCLK (void);
unsigned long get_UCLK (void);
#endif
#if defined(CONFIG_LH7A40X)
unsigned long get_PLLCLK (void);
#endif
#if defined CONFIG_INCA_IP
unsigned int incaip_get_cpuclk (void);
#endif
#if defined(CONFIG_IMX)
unsigned long get_systemPLLCLK(void);
unsigned long get_FCLK(void);
unsigned long get_HCLK(void);
unsigned long get_BCLK(void);
unsigned long get_PERCLK1(void);
unsigned long get_PERCLK2(void);
unsigned long get_PERCLK3(void);
#endif
unsigned long get_bus_freq (unsigned long);
int get_serial_clock(void);
struct pt_regs;
/* $(CPU)/interrupts.c */
int interrupt_init (void);
void timer_interrupt (struct pt_regs *);
void external_interrupt (struct pt_regs *);
void irq_install_handler(int, interrupt_handler_t *, void *);
void irq_free_handler (int);
void reset_timer (void);
unsigned long get_timer (unsigned long base);
void enable_interrupts (void);
int disable_interrupts (void);
/* $(CPU)/.../commproc.c */
int dpram_init (void);
unsigned int dpram_base(void);
unsigned int dpram_base_align(unsigned int align);
unsigned int dpram_alloc(unsigned int size);
unsigned int dpram_alloc_align(unsigned int size,unsigned int align);
void bootcount_store (unsigned long);
unsigned long bootcount_load (void);
#define BOOTCOUNT_MAGIC 0xB001C041
/* $(CPU)/.../<eth> */
void mii_init (void);
/* $(CPU)/.../lcd.c */
unsigned long lcd_setmem (unsigned long);
/* $(CPU)/.../video.c */
unsigned long video_setmem (unsigned long);
/* arch/$(ARCH)/lib/cache.c */
unsigned long dcache_get_line_size(void);
void enable_caches(void);
void flush_cache (unsigned long, unsigned long);
void flush_dcache_all(void);
void flush_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_all(void);
void invalidate_icache_all(void);
/* arch/$(ARCH)/lib/ticks.S */
unsigned long long get_ticks(void);
void wait_ticks (unsigned long);
/* arch/$(ARCH)/lib/time.c */
void __udelay (unsigned long);
unsigned long usec2ticks (unsigned long usec);
unsigned long ticks2usec (unsigned long ticks);
int init_timebase (void);
/* lib/qsort.c */
void qsort(void *base, size_t nmemb, size_t size,
int(*compar)(const void *, const void *));
int strcmp_compar(const void *, const void *);
/* lib/time.c */
void udelay (unsigned long);
/* Multicore arch functions */
#ifdef CONFIG_MP
int cpu_status(int nr);
int cpu_reset(int nr);
int cpu_disable(int nr);
int cpu_release(int nr, int argc, char * const argv[]);
#endif
#endif /* __ASSEMBLER__ */
/* Put only stuff here that the assembler can digest */
#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1))
#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
//#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#endif /* __COMMON_H_ */

1
src/arch/armv7/lib/eabi_compat.c
View File

@ -9,7 +9,6 @@
* License, or (at your option) any later version.
*/
#include <common.h>
#include <console/console.h>
/* FIXME(dhendrix): prototypes added for assembler */

1
src/arch/armv7/lib/interrupts.c
View File

@ -35,7 +35,6 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <reset.h>
DECLARE_GLOBAL_DATA_PTR;

1
src/arch/armv7/stages.c
View File

@ -32,7 +32,6 @@
*/
#include <arch/stages.h>
#include <arch/armv7/include/common.h>
#include <arch/cache.h>
void stage_entry(void)

1
src/cpu/armltd/cortex-a9/cache.c
View File

@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
#include <common.h>
#include <armv7.h>
/*

4
src/cpu/samsung/exynos5250/Kconfig
View File

@ -10,10 +10,6 @@ config EXYNOS_ACE_SHA
bool
default n
config SATA_AHCI
bool
default n
config BL1_SIZE_KB
int
default 8

16
src/cpu/samsung/exynos5250/Makefile.inc
View File

@ -9,7 +9,6 @@ bootblock-y += pinmux.c mct.c power.c
bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c
bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c
bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c
bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c
bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
bootblock-y += wakeup.c
bootblock-y += gpio.c
@ -19,13 +18,12 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += timer.c
romstage-y += spi.c
romstage-y += clock.c
romstage-y += clock_init.c
romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart.
romstage-y += pinmux.c # required by s3c24x0_i2c and uart.
romstage-y += dmc_common.c
romstage-y += dmc_init_ddr3.c
romstage-y += power.c
romstage-y += mct.c
romstage-y += monotonic_timer.c
romstage-$(CONFIG_EARLY_CONSOLE) += soc.c
romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
romstage-y += wakeup.c
romstage-y += pwm.c # needed by timer.c
@ -33,29 +31,23 @@ romstage-y += gpio.c
romstage-y += timer.c
romstage-y += i2c.c
#romstage-y += wdt.c
#romstage-y += sromc.c
ramstage-y += spi.c
#ramstage-y += tzpc_init.c
ramstage-y += clock.c
ramstage-y += clock_init.c
ramstage-y += pinmux.c
ramstage-y += power.c
ramstage-y += soc.c
ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
ramstage-y += cpu.c
ramstage-y += exynos5250-tmu.c
ramstage-y += tmu.c
ramstage-y += mct.c
ramstage-y += monotonic_timer.c
#ramstage-$(CONFIG_SATA_AHCI) += sata.c
ramstage-y += cpu_info.c
ramstage-y += pwm.c # needed by timer.c
ramstage-y += timer.c
ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += s5p-dp-reg.c
ramstage-y += exynos-fb.c
ramstage-y += exynos-tmu.c
ramstage-y += dp-reg.c
ramstage-y += fb.c
exynos5250_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5250 BL1\n"

42
src/cpu/samsung/exynos5250/adc.h
View File

@ -1,42 +0,0 @@
/*
* Copyright (C) 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* MyungJoo Ham <myungjoo.ham@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_COMMON_ADC_H_
#define __ASM_ARM_ARCH_COMMON_ADC_H_
#ifndef __ASSEMBLER__
struct s5p_adc {
unsigned int adccon;
unsigned int adctsc;
unsigned int adcdly;
unsigned int adcdat0;
unsigned int adcdat1;
unsigned int adcupdn;
unsigned int adcclrint;
unsigned int adcmux;
unsigned int adcclrintpndnup;
};
#endif
#endif /* __ASM_ARM_ARCH_COMMON_ADC_H_ */

2
src/cpu/samsung/exynos5250/bootblock.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 The Chromium OS Authors
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

100
src/cpu/samsung/exynos5250/clk.h
View File

@ -1,11 +1,12 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright 2013 Google Inc.
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,15 +15,12 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS5_CLK_H__
#define __EXYNOS5_CLK_H__
#ifndef CPU_SAMSUNG_EXYNOS5250_CLK_H
#define CPU_SAMSUNG_EXYNOS5250_CLK_H
#include <types.h>
#include <stdint.h>
enum periph_id;
@ -66,7 +64,7 @@ void set_mmc_clk(int dev_index, unsigned int div);
*/
unsigned long clock_get_periph_rate(enum periph_id peripheral);
#include <cpu/samsung/exynos5250/pinmux.h>
#include "pinmux.h"
#define MCT_ADDRESS 0x101c0000
@ -107,8 +105,6 @@ void clock_select_i2s_clk_source(void);
*/
int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
/* FIXME(dhendrix): below is stuff from arch/arm/include/asm/arch-exynos5/clock.h
(as opposed to the two clk.h files as they were named in u-boot... */
struct exynos5_clock {
unsigned int apll_lock; /* base + 0 */
unsigned char res1[0xfc];
@ -585,50 +581,44 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor);
*/
int clock_set_rate(enum periph_id periph_id, unsigned int rate);
/**
* Decode a peripheral ID from a device node.
*
* Drivers should always use this function since the actual means of
* encoding this information may change in the future as fdt support for
* exynos evolves.
*
* @param blob FDT blob to read from
* @param node Node containing the information
*/
int clock_decode_periph_id(const void *blob, int node);
/* Clock gate unused IP */
void clock_gate(void);
enum ddr_mode;
enum mem_manuf;
const char *clock_get_mem_type_name(enum ddr_mode mem_type);
const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf);
/*
* TODO(sjg@chromium.org): Remove this when we have more SPL space.
* At present we are using 14148 of 14336 bytes. If we change this function
* to be exported in SPL, we go over the edge.
*/
/**
* Get the required memory type and speed (Main U-Boot version).
*
* This should use the device tree. For now we cannot since this function is
* called before the FDT is available.
*
* @param mem_type Returns memory type
* @param frequency_mhz Returns memory speed in MHz
* @param arm_freq Returns ARM clock speed in MHz
* @param mem_manuf Return Memory Manufacturer name
* @return 0 if all ok (if not, this function currently does not return)
*/
int clock_get_mem_selection(enum ddr_mode *mem_type,
unsigned *frequency_mhz, unsigned *arm_freq,
enum mem_manuf *mem_manuf);
void mct_start(void);
uint64_t mct_raw_value(void);
#include "dmc.h"
/* These are the ratio's for configuring ARM clock */
struct arm_clk_ratios {
unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */
unsigned int apll_mdiv;
unsigned int apll_pdiv;
unsigned int apll_sdiv;
unsigned int arm2_ratio;
unsigned int apll_ratio;
unsigned int pclk_dbg_ratio;
unsigned int atb_ratio;
unsigned int periph_ratio;
unsigned int acp_ratio;
unsigned int cpud_ratio;
unsigned int arm_ratio;
};
/**
* Get the clock ratios for CPU configuration
*
* @return pointer to the clock ratios that we should use
*/
struct arm_clk_ratios *get_arm_clk_ratios(void);
/*
* Initialize clock for the device
*/
struct mem_timings;
void system_clock_init(struct mem_timings *mem,
struct arm_clk_ratios *arm_clk_ratio);
#endif

71
src/cpu/samsung/exynos5250/clock.c
View File

@ -1,14 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -17,23 +14,21 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
#include <console/console.h>
#include <stdlib.h>
//#include <fdtdec.h>
#include <assert.h>
#include <arch/io.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/clock_init.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include "timer.h"
#include "clk.h"
#include "cpu.h"
/* input clock of PLL: SMDK5250 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
struct arm_clk_ratios arm_clk_ratios[] = {
static struct arm_clk_ratios arm_clk_ratios[] = {
{
.arm_freq_mhz = 600,
@ -438,7 +433,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
shift = 16;
break;
default:
debug("%s: Unsupported peripheral ID %d\n", __func__,
printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
periph_id);
return;
}
@ -475,7 +470,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
shift = 12;
break;
default:
debug("%s: Unsupported peripheral ID %d\n", __func__,
printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
periph_id);
return;
}
@ -507,11 +502,11 @@ static int clock_calc_best_scalar(unsigned int main_scaler_bits,
const unsigned int cap = (1 << fine_scalar_bits) - 1;
const unsigned int loops = 1 << main_scaler_bits;
debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
printk(BIOS_DEBUG, "Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
target_rate, cap);
assert(best_fine_scalar != NULL);
assert(main_scaler_bits <= fine_scalar_bits);
ASSERT(best_fine_scalar != NULL);
ASSERT(main_scaler_bits <= fine_scalar_bits);
*best_fine_scalar = 1;
@ -528,7 +523,7 @@ static int clock_calc_best_scalar(unsigned int main_scaler_bits,
effective_div;
const int error = target_rate - effective_rate;
debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
printk(BIOS_DEBUG, "%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
effective_rate, error);
if (error >= 0 && error <= best_error) {
@ -554,7 +549,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate)
case PERIPH_ID_SPI4:
main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
if (main < 0) {
debug("%s: Cannot set clock rate for periph %d",
printk(BIOS_DEBUG, "%s: Cannot set clock rate for periph %d",
__func__, periph_id);
return -1;
}
@ -562,7 +557,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate)
clock_ll_set_pre_ratio(periph_id, fine - 1);
break;
default:
debug("%s: Unsupported peripheral ID %d\n", __func__,
printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
periph_id);
return -1;
}
@ -596,7 +591,7 @@ int clock_set_mshci(enum periph_id peripheral)
addr = &clk->div_fsys2;
break;
default:
debug("invalid peripheral\n");
printk(BIOS_DEBUG, "invalid peripheral\n");
return -1;
}
tmp = readl(addr) & ~0xff0f;
@ -609,24 +604,6 @@ int clock_set_mshci(enum periph_id peripheral)
return 0;
}
#ifdef CONFIG_OF_CONTROL
int clock_decode_periph_id(const void *blob, int node)
{
enum periph_id id;
/*
* For now the peripheral ID is directly encoded. Once we have clock
* support in the fdt and properly in exynos U-Boot we may have
* another way of changing the clock.
*/
id = fdtdec_get_int(blob, node, "samsung,periph-id", -1);
assert(id != PERIPH_ID_NONE);
assert(id >= 0 && id < PERIPH_ID_COUNT);
return id;
}
#endif
int clock_epll_set_rate(unsigned long rate)
{
unsigned int epll_con, epll_con_k;
@ -697,15 +674,15 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
unsigned int div ;
if ((dst_frq == 0) || (src_frq == 0)) {
debug("%s: Invalid requency input for prescaler\n", __func__);
debug("src frq = %d des frq = %d ", src_frq, dst_frq);
printk(BIOS_DEBUG, "%s: Invalid requency input for prescaler\n", __func__);
printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
return -1;
}
div = (src_frq / dst_frq);
if (div > AUDIO_1_RATIO_MASK) {
debug("%s: Frequency ratio is out of range\n", __func__);
debug("src frq = %d des frq = %d ", src_frq, dst_frq);
printk(BIOS_DEBUG, "%s: Frequency ratio is out of range\n", __func__);
printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
return -1;
}
clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,

94
src/cpu/samsung/exynos5250/clock.h
View File

@ -1,94 +0,0 @@
/*
* (C) Copyright 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Heungjun Kim <riverful.kim@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __ASM_ARM_ARCH_CLOCK_H_
#define __ASM_ARM_ARCH_CLOCK_H_
#ifndef __ASSEMBLER__
struct s5pc100_clock {
unsigned int apll_lock;
unsigned int mpll_lock;
unsigned int epll_lock;
unsigned int hpll_lock;
unsigned char res1[0xf0];
unsigned int apll_con;
unsigned int mpll_con;
unsigned int epll_con;
unsigned int hpll_con;
unsigned char res2[0xf0];
unsigned int src0;
unsigned int src1;
unsigned int src2;
unsigned int src3;
unsigned char res3[0xf0];
unsigned int div0;
unsigned int div1;
unsigned int div2;
unsigned int div3;
unsigned int div4;
unsigned char res4[0x1ec];
unsigned int gate_d00;
unsigned int gate_d01;
unsigned int gate_d02;
unsigned char res5[0x54];
unsigned int gate_sclk0;
unsigned int gate_sclk1;
};
struct s5pc110_clock {
unsigned int apll_lock;
unsigned char res1[0x4];
unsigned int mpll_lock;
unsigned char res2[0x4];
unsigned int epll_lock;
unsigned char res3[0xc];
unsigned int vpll_lock;
unsigned char res4[0xdc];
unsigned int apll_con;
unsigned char res5[0x4];
unsigned int mpll_con;
unsigned char res6[0x4];
unsigned int epll_con;
unsigned char res7[0xc];
unsigned int vpll_con;
unsigned char res8[0xdc];
unsigned int src0;
unsigned int src1;
unsigned int src2;
unsigned int src3;
unsigned char res9[0xf0];
unsigned int div0;
unsigned int div1;
unsigned int div2;
unsigned int div3;
unsigned int div4;
unsigned char res10[0x1ec];
unsigned int gate_d00;
unsigned int gate_d01;
unsigned int gate_d02;
unsigned char res11[0x54];
unsigned int gate_sclk0;
unsigned int gate_sclk1;
};
#endif
#endif

31
src/cpu/samsung/exynos5250/clock_init.c
View File

@ -1,15 +1,11 @@
/*
* Clock setup for SMDK5250 board based on EXYNOS5
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,23 +14,16 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <delay.h>
#include <stdlib.h>
#include <types.h>
/* Clock setup for SMDK5250 board based on EXYNOS5 */
#include <console/console.h>
/* FIXME: remove unneeded #includes */
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/clock_init.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/dmc.h>
#include <cpu/samsung/exynos5250/s5p-dp.h>
#include <delay.h>
#include "clk.h"
#include "cpu.h"
#include "dp.h"
#include "setup.h"
void system_clock_init(struct mem_timings *mem,

60
src/cpu/samsung/exynos5250/clock_init.h
View File

@ -1,60 +0,0 @@
/*
* Clock initialization routines
*
* Copyright (c) 2011 The Chromium OS Authors.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __EXYNOS_CLOCK_INIT_H
#define __EXYNOS_CLOCK_INIT_H
#include "dmc.h"
/* These are the ratio's for configuring ARM clock */
struct arm_clk_ratios {
unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */
unsigned int apll_mdiv;
unsigned int apll_pdiv;
unsigned int apll_sdiv;
unsigned int arm2_ratio;
unsigned int apll_ratio;
unsigned int pclk_dbg_ratio;
unsigned int atb_ratio;
unsigned int periph_ratio;
unsigned int acp_ratio;
unsigned int cpud_ratio;
unsigned int arm_ratio;
};
/**
* Get the clock ratios for CPU configuration
*
* @return pointer to the clock ratios that we should use
*/
struct arm_clk_ratios *get_arm_clk_ratios(void);
/*
* Initialize clock for the device
*/
struct mem_timings;
void system_clock_init(struct mem_timings *mem,
struct arm_clk_ratios *arm_clk_ratio);
#endif

56
src/cpu/samsung/exynos5250/cpu.c
View File

@ -1,3 +1,22 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdlib.h>
#include <string.h>
#include <stddef.h>
@ -6,15 +25,35 @@
#include <device/device.h>
#include <cbmem.h>
#include <arch/cache.h>
#include <cpu/samsung/exynos5250/fimd.h>
#include <cpu/samsung/exynos5250/s5p-dp-core.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include "chip.h"
#include "fimd.h"
#include "dp-core.h"
#include "cpu.h"
#include "clk.h"
#include "chip.h"
#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
static unsigned int cpu_id;
static unsigned int cpu_rev;
static void set_cpu_id(void)
{
cpu_id = readl((void *)EXYNOS_PRO_ID);
cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12));
/*
* 0xC200: EXYNOS4210 EVT0
* 0xC210: EXYNOS4210 EVT1
*/
if (cpu_id == 0xC200) {
cpu_id |= 0x10;
cpu_rev = 0;
} else if (cpu_id == 0xC210) {
cpu_rev = 1;
}
}
/* we distinguish a display port device from a raw graphics device
* because there are dramatic differences in startup depending on
* graphics usage. To make startup fast and easier to understand and
@ -64,7 +103,7 @@ static void exynos_displayport_init(device_t dev)
*/
fb_size = conf->xres * conf->yres * (conf->bpp / 8);
lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB);
printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase));
printk(BIOS_SPEW, "LCD colormap base is %p\n", (void *)(lcdbase));
mmio_resource(dev, 0, lcdbase/KiB, 64);
vi.cmap = (void *)lcdbase;
@ -89,7 +128,7 @@ static void exynos_displayport_init(device_t dev)
lcdbase += 64*KiB;
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
"Initializing exynos VGA, base %p\n", (void *)lcdbase);
"Initializing Exynos VGA, base %p\n", (void *)lcdbase);
memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase);
}
@ -99,7 +138,10 @@ static void cpu_init(device_t dev)
exynos_displayport_init(dev);
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
arch_cpu_init();
set_cpu_id();
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
cpu_id, get_arm_clk() / (1024*1024));
}
static void cpu_noop(device_t dev)

105
src/cpu/samsung/exynos5250/cpu.h
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (C) 2010 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,49 +14,11 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _EXYNOS5250_CPU_H
#define _EXYNOS5250_CPU_H
#define S5PC1XX_ADDR_BASE 0xE0000000
/* S5PC100 */
#define S5PC100_PRO_ID 0xE0000000
#define S5PC100_CLOCK_BASE 0xE0100000
#define S5PC100_GPIO_BASE 0xE0300000
#define S5PC100_VIC0_BASE 0xE4000000
#define S5PC100_VIC1_BASE 0xE4100000
#define S5PC100_VIC2_BASE 0xE4200000
#define S5PC100_DMC_BASE 0xE6000000
#define S5PC100_SROMC_BASE 0xE7000000
#define S5PC100_ONENAND_BASE 0xE7100000
#define S5PC100_PWMTIMER_BASE 0xEA000000
#define S5PC100_WATCHDOG_BASE 0xEA200000
#define S5PC100_UART_BASE 0xEC000000
#define S5PC100_MMC_BASE 0xED800000
/* S5PC110 */
#define S5PC110_PRO_ID 0xE0000000
#define S5PC110_CLOCK_BASE 0xE0100000
#define S5PC110_GPIO_BASE 0xE0200000
#define S5PC110_PWMTIMER_BASE 0xE2500000
#define S5PC110_WATCHDOG_BASE 0xE2700000
#define S5PC110_UART_BASE 0xE2900000
#define S5PC110_SROMC_BASE 0xE8000000
#define S5PC110_MMC_BASE 0xEB000000
#define S5PC110_DMC0_BASE 0xF0000000
#define S5PC110_DMC1_BASE 0xF1400000
#define S5PC110_VIC0_BASE 0xF2000000
#define S5PC110_VIC1_BASE 0xF2100000
#define S5PC110_VIC2_BASE 0xF2200000
#define S5PC110_VIC3_BASE 0xF2300000
#define S5PC110_OTG_BASE 0xEC000000
#define S5PC110_PHY_BASE 0xEC100000
#define S5PC110_USB_PHY_CONTROL 0xE010E80C
#ifndef CPU_SAMSUNG_EXYNOS5250_CPU_H
#define CPU_SAMSUNG_EXYNOS5250_CPU_H
#include <arch/io.h>
@ -80,48 +42,6 @@
#define EXYNOS_I2C_SPACING 0x10000
enum boot_mode {
/*
* Assign the OM pin values for respective boot modes.
* Exynos4 does not support spi boot and the mmc boot OM
* pin values are the same across Exynos4 and Exynos5.
*/
BOOT_MODE_MMC = 4,
BOOT_MODE_SERIAL = 20,
/* Boot based on Operating Mode pin settings */
BOOT_MODE_OM = 32,
BOOT_MODE_USB, /* Boot using USB download */
};
/**
* Get the boot device containing BL1, BL2 (SPL) and U-boot
*
* @return boot device
*/
enum boot_mode exynos_get_boot_device(void);
/**
* Check if a wakeup is permitted.
*
* On some boards we need to look at a special GPIO to ensure that the wakeup
* from sleep was valid. If the wakeup is not valid we need to go through a
* full reset.
*
* The default implementation of this function allows all wakeups.
*
* @return 1 if wakeup is permitted; 0 otherwise
*/
int board_wakeup_permitted(void);
/**
* Init subsystems according to the reset status
*
* @return 0 for a normal boot, non-zero for a resume
*/
int lowlevel_init_subsystems(void);
int arch_cpu_init(void);
/* EXYNOS5 */
#define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */
#define EXYNOS5_PRO_ID 0x10000000
@ -144,21 +64,17 @@ int arch_cpu_init(void);
#define EXYNOS5_USBPHY_BASE 0x12130000
#define EXYNOS5_USBOTG_BASE 0x12140000
#ifndef CONFIG_OF_CONTROL
#define EXYNOS5_MMC_BASE 0x12200000
#define EXYNOS5_MSHC_BASE 0x12240000
#endif
#define EXYNOS5_SROMC_BASE 0x12250000
#define EXYNOS5_UART_BASE 0x12C00000
#define EXYNOS5_SPI1_BASE 0x12D30000
#ifndef CONFIG_OF_CONTROL
#define EXYNOS5_I2C_BASE 0x12C60000
#define EXYNOS5_SPI_BASE 0x12D20000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_SPI_ISP_BASE 0x131A0000
#endif
#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_GPIO_PART3_BASE 0x13400000 /* E00..H17 */
#define EXYNOS5_FIMD_BASE 0x14400000
@ -213,9 +129,6 @@ int arch_cpu_init(void);
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
#define EXYNOS_I2C_MAX_CONTROLLERS 8
/* helper function to map mmio address to peripheral id */
enum periph_id exynos5_get_periph_id(unsigned base_addr);
void exynos5250_config_l2_cache(void);
extern struct tmu_info exynos5250_tmu_info;

64
src/cpu/samsung/exynos5250/cpu_info.c
View File

@ -1,64 +0,0 @@
/*
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <console/console.h>
#include <common.h>
#include <arch/io.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/clock.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/dmc.h>
/* FIXME(dhendrix): consolidate samsung ID code/#defines to a common location */
#include <cpu/samsung/exynos5250/setup.h> /* cpu_info_init() prototype */
static unsigned int s5p_cpu_id;
static unsigned int s5p_cpu_rev;
static void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl((void *)EXYNOS_PRO_ID);
s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
/*
* 0xC200: EXYNOS4210 EVT0
* 0xC210: EXYNOS4210 EVT1
*/
if (s5p_cpu_id == 0xC200) {
s5p_cpu_id |= 0x10;
s5p_cpu_rev = 0;
} else if (s5p_cpu_id == 0xC210) {
s5p_cpu_rev = 1;
}
}
int arch_cpu_init(void)
{
s5p_set_cpu_id();
printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n",
s5p_cpu_id, get_arm_clk() / (1024*1024));
return 0;
}

21
src/cpu/samsung/exynos5250/dmc.h
View File

@ -1,5 +1,22 @@
#ifndef __DMC_H__
#define __DMC_H__
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef CPU_SAMSUNG_EXYNOS5250_DMC_H
#define CPU_SAMSUNG_EXYNOS5250_DMC_H
#ifndef __ASSEMBLER__
struct exynos5_dmc {

31
src/cpu/samsung/exynos5250/dmc_common.c
View File

@ -1,15 +1,11 @@
/*
* Mem setup common file for different types of DDR present on SMDK5250 boards.
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,19 +14,18 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <assert.h>
#include <delay.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/dmc.h>
#include <cpu/samsung/exynos5250/clock_init.h>
/* Mem setup common file for different types of DDR present on SMDK5250 boards.
*/
#include "clock_init.h"
#include <console/console.h>
#include <arch/io.h>
#include <delay.h>
#include "setup.h"
#include "dmc.h"
#include "clk.h"
#include "setup.h"
#define ZQ_INIT_TIMEOUT 10000

23
src/cpu/samsung/exynos5250/dmc_init_ddr3.c
View File

@ -1,15 +1,11 @@
/*
* DDR3 mem setup file for SMDK5250 board based on EXYNOS5
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,21 +14,18 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <config.h>
/* DDR3 mem setup file for SMDK5250 board based on EXYNOS5 */
#include <console/console.h>
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
/* FIXME(dhendrix): untangle clock/clk ... */
#include <cpu/samsung/exynos5250/clock.h>
#include "clk.h"
#include "cpu.h"
#include "dmc.h"
#include "setup.h"
#include "clock_init.h"
#define RDLVL_COMPLETE_TIMEOUT 10000

29
src/cpu/samsung/exynos5250/s5p-dp-core.h → src/cpu/samsung/exynos5250/dp-core.h
View File

@ -1,18 +1,27 @@
/*
* Header file for Samsung DP (Display Port) interface driver.
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com>
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _S5P_DP_CORE_H
#define _S5P_DP_CORE_H
/* Header file for Samsung DP (Display Port) interface driver. */
#ifndef CPU_SAMSUNG_EXYNOS5250_DP_CORE_H
#define CPU_SAMSUNG_EXYNOS5250_DP_CORE_H
#define STREAM_ON_TIMEOUT 100
#define PLL_LOCK_TIMEOUT 10
@ -256,4 +265,4 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase,
int dp_controller_init(struct s5p_dp_device *dp_device);
int lcd_ctrl_init(vidinfo_t *panel_info,
struct exynos5_fimd_panel *panel_data, void *lcdbase);
#endif /* _S5P_DP_CORE_H */
#endif /* CPU_SAMSUNG_EXYNOS5250_DP_CORE_H */

39
src/cpu/samsung/exynos5250/s5p-dp-reg.c → src/cpu/samsung/exynos5250/dp-reg.c
View File

@ -1,25 +1,34 @@
/*
* Samsung DP (Display port) register interface driver.
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <jg1.han@samsung.com>
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
#include <arch/io.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/s5p-dp.h>
#include "cpu/samsung/exynos5250/fimd.h"
#include "s5p-dp-core.h"
/* Samsung DP (Display port) register interface driver. */
#include <console/console.h>
#include <arch/io.h>
#include <delay.h>
#include "timer.h"
#include "clk.h"
#include "cpu.h"
#include "periph.h"
#include "dp.h"
#include "fimd.h"
#include "dp-core.h"
void s5p_dp_reset(struct s5p_dp_device *dp)
{

41
src/cpu/samsung/exynos5250/s5p-dp.h → src/cpu/samsung/exynos5250/dp.h
View File

@ -1,12 +1,12 @@
/*
* Copyright 2013 Google Inc.
* (C) Copyright 2012 Samsung Electronics
* Register map for Exynos5 DP
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright 2013 Google Inc.
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -15,12 +15,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS5_DP_H__
#define __EXYNOS5_DP_H__
/* Register map for Exynos5 DP */
#ifndef CPU_SAMSUNG_EXYNOS5250_DP_H
#define CPU_SAMSUNG_EXYNOS5250_DP_H
/* DSIM register map */
struct exynos5_dp {
@ -493,22 +494,4 @@ struct exynos5_dp {
/* Allow DP Gating clock and set FIMD source to 267 Mhz for DP */
void clock_init_dp_clock(void);
/**
* Perform the next stage of the LCD init if it is time to do so.
*
* LCD init can be time-consuming because of the number of delays we need
* while waiting for the backlight power supply, etc. This function can
* be called at various times during U-Boot operation to advance the
* initialization of the LCD to the next stage if sufficient time has
* passed since the last stage. It keeps track of what stage it is up to
* and the time that it is permitted to move to the next stage.
*
* The final call should have can_block=1 to complete the init.
*
* @param blob fdt blob containing LCD information
* @param can_block 1 to wait until all init is complete, and then return
* 0 to return immediately, potentially doing nothing if it
* is not yet time for the next init.
*/
int exynos_lcd_check_next_stage(const void *blob, int can_block);
#endif

21
src/cpu/samsung/exynos5250/dsim.h
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Register map for Exynos5 MIPI-DSIM
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,12 +14,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS5_DSIM_H__
#define __EXYNOS5_DSIM_H__
/* Register map for Exynos5 MIPI-DSIM */
#ifndef CPU_SAMSUNG_EXYNOS5250_DSIM_H
#define CPU_SAMSUNG_EXYNOS5250_DSIM_H
/* DSIM register map */
struct exynos5_dsim {

54
src/cpu/samsung/exynos5250/exynos-cpufreq.h
View File

@ -1,54 +0,0 @@
/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - CPU frequency scaling support
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Define various levels of ARM frequency */
enum cpufreq_level {
CPU_FREQ_L200, /* 200 MHz */
CPU_FREQ_L300, /* 300 MHz */
CPU_FREQ_L400, /* 400 MHz */
CPU_FREQ_L500, /* 500 MHz */
CPU_FREQ_L600, /* 600 MHz */
CPU_FREQ_L700, /* 700 MHz */
CPU_FREQ_L800, /* 800 MHz */
CPU_FREQ_L900, /* 900 MHz */
CPU_FREQ_L1000, /* 1000 MHz */
CPU_FREQ_L1100, /* 1100 MHz */
CPU_FREQ_L1200, /* 1200 MHz */
CPU_FREQ_L1300, /* 1300 MHz */
CPU_FREQ_L1400, /* 1400 MHz */
CPU_FREQ_L1500, /* 1500 MHz */
CPU_FREQ_L1600, /* 1600 MHz */
CPU_FREQ_L1700, /* 1700 MHz */
CPU_FREQ_LCOUNT,
};
/*
* Initialize ARM frequency scaling
*
* @param blob FDT blob
* @return int value, 0 for success
*/
int exynos5250_cpufreq_init(const void *blob);
/*
* Switch ARM frequency to new level
*
* @param new_freq_level enum cpufreq_level, states new frequency
* @return int value, 0 for success
*/
int exynos5250_set_frequency(enum cpufreq_level new_freq_level);

45
src/cpu/samsung/exynos5250/exynos5-common.h
View File

@ -1,45 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* Common configuration settings for EXYNOS5 based boards.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __EXYNOS5_CONFIG_H
#define __EXYNOS5_CONFIG_H
#include <cpu/samsung/exynos5250/cpu.h> /* get chip and board defs */
/* TODO(dhendrix): some #defines are commented out here and moved to Kconfig */
//#define CONFIG_SYS_SDRAM_BASE 0x40000000
//#define CONFIG_SYS_TEXT_BASE 0x43e00000
/* Power Down Modes */
#define S5P_CHECK_SLEEP 0x00000BAD
#define S5P_CHECK_DIDLE 0xBAD00000
#define S5P_CHECK_LPA 0xABAD0000
#define CONFIG_SYS_HZ 1000
/* We spend about 100us getting from reset to SPL */
#define CONFIG_SPL_TIME_US 100000
#endif /* __EXYNOS5_CONFIG_H */

45
src/cpu/samsung/exynos5250/exynos5250-tmu.c
View File

@ -1,45 +0,0 @@
/*
* Copyright (C) 2013 Google Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This file contains Exynos5250-specific TMU information.
*/
#include <cpu/samsung/exynos5250/exynos-tmu.h>
#include <cpu/samsung/exynos5250/cpu.h>
struct tmu_info exynos5250_tmu_info = {
.tmu_base = 0x10060000,
.tmu_mux = 6,
.data = {
.ts = {
.min_val = 25,
.max_val = 125,
.start_warning = 95,
.start_tripping = 105,
.hardware_tripping = 110,
},
.efuse_min_value = 40,
.efuse_value = 55,
.efuse_max_value = 100,
.slope = 0x10008802,
},
.dc_value = 25,
};

47
src/cpu/samsung/exynos5250/exynos-fb.c → src/cpu/samsung/exynos5250/fb.c
View File

@ -1,46 +1,42 @@
/*
* LCD driver for Exynos
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
/* LCD driver for Exynos */
#include <arch/io.h>
#include <stdlib.h>
#include <string.h>
#include <timer.h>
#include <delay.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/sysreg.h>
#include "timer.h"
#include "cpu.h"
#include "power.h"
#include "sysreg.h"
#include <drivers/maxim/max77686/max77686.h>
#include "device/i2c.h"
#include "cpu/samsung/exynos5250/i2c.h"
#include "cpu/samsung/exynos5250/dsim.h"
#include "cpu/samsung/exynos5250/fimd.h"
#include "cpu/samsung/exynos5250/s5p-dp.h"
#include "s5p-dp-core.h"
#include "i2c.h"
#include "fimd.h"
#include "dp.h"
#include "dp-core.h"
/*
* Here is the rough outline of how we bring up the display:
@ -111,12 +107,6 @@ void *lcd_console_address; /* Start of console buffer */
short console_col;
short console_row;
#ifdef CONFIG_EXYNOS_DISPLAYPORT
static struct s5p_dp_device dp_device;
#endif
/* Bypass FIMD of DISP1_BLK */
static void fimd_bypass(void)
{
@ -192,7 +182,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase,
writel(1 << 1, &fimd->dpclkcon);
}
void exynos_fimd_disable(void);
#ifdef UNUSED_CODE
void exynos_fimd_disable(void)
{
struct exynos5_fimd *fimd = samsung_get_base_fimd();
@ -200,6 +190,7 @@ void exynos_fimd_disable(void)
writel(0, &fimd->wincon0);
clrbits_le32(&fimd->shadowcon, CHANNEL0_EN);
}
#endif
/*
* Configure DP in slave mode and wait for video stream.

25
src/cpu/samsung/exynos5250/fet.h
View File

@ -1,25 +0,0 @@
/*
* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*/
#ifndef __ASM_ARM_ARCH_EXYNOS5_FET_H
#define __ASM_ARM_ARCH_EXYNOS5_FET_H
/* The FET IDs for TPS65090 PMU chip. */
enum {
FET_ID_BL = 1
FET_ID_VIDEO,
FET_ID_WWAN,
FET_ID_SDCARD,
FET_ID_CAMOUT,
FET_ID_LCD,
FET_ID_TS
};
#endif

21
src/cpu/samsung/exynos5250/fimd.h
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Register map for Exynos5 FIMD
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,12 +14,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS5_FIMD_H__
#define __EXYNOS5_FIMD_H__
/* Register map for Exynos5 FIMD */
#ifndef CPU_SAMSUNG_EXYNOS5250_FIMD_H
#define CPU_SAMSUNG_EXYNOS5250_FIMD_H
/* FIMD register map */
struct exynos5_fimd {

156
src/cpu/samsung/exynos5250/gpio.c
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (C) 2009 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,18 +14,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* FIXME(dhendrix): fix this up so it doesn't require a bunch of #ifdefs... */
#include <common.h>
#include <gpio.h>
//#include <arch/io.h>
#include <gpio.h>
#include <arch/gpio.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/gpio.h> /* FIXME: for gpio_decode_number prototype */
#include <string.h>
#include <delay.h>
#include <assert.h>
#include "gpio.h"
#include "cpu.h"
#define CON_MASK(x) (0xf << ((x) << 2))
#define CON_SFR(x, v) ((v) << ((x) << 2))
@ -46,7 +43,6 @@ struct gpio_info {
unsigned int max_gpio; /* Maximum GPIO in this part */
};
#include <cpu/samsung/exynos5250/cpu.h>
static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = {
{ EXYNOS5_GPIO_PART1_BASE, GPIO_MAX_PORT_PART_1 },
{ EXYNOS5_GPIO_PART2_BASE, GPIO_MAX_PORT_PART_2 },
@ -56,12 +52,9 @@ static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = {
{ EXYNOS5_GPIO_PART6_BASE, GPIO_MAX_PORT },
};
#define HAVE_GENERIC_GPIO
/* This macro gets gpio pin offset from 0..7 */
#define GPIO_BIT(x) ((x) & 0x7)
//#ifdef HAVE_GENERIC_GPIO
static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio)
{
const struct gpio_info *data;
@ -79,10 +72,9 @@ static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio)
}
}
assert(gpio < GPIO_MAX_PORT); /* ...which it will not be */
ASSERT(gpio < GPIO_MAX_PORT); /* ...which it will not be */
return NULL;
}
//#endif
/* TODO: Deprecation this interface in favour of asm-generic/gpio.h */
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
@ -192,10 +184,6 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
}
/* Common GPIO API - only available on Exynos5 */
/* FIXME(dhendrix): If this stuff is really only applicable to exynos5,
move it to a more sensible location. */
#ifdef HAVE_GENERIC_GPIO
void gpio_cfg_pin(int gpio, int cfg)
{
unsigned int value;
@ -277,16 +265,6 @@ void gpio_set_rate(int gpio, int mode)
writel(value, &bank->drv);
}
int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
int gpio_free(unsigned gpio)
{
return 0;
}
int gpio_direction_input(unsigned gpio)
{
gpio_cfg_pin(gpio, EXYNOS_GPIO_INPUT);
@ -332,64 +310,6 @@ int gpio_set_value(unsigned gpio, int value)
return 0;
}
#else
static int s5p_gpio_get_pin(unsigned gpio)
{
return gpio % GPIO_PER_BANK;
}
/*
* If we have the old-style GPIO numbering setup, use these functions
* which don't necessary provide sequentially increasing GPIO numbers.
*/
static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
{
int bank = gpio / GPIO_PER_BANK;
bank *= sizeof(struct s5p_gpio_bank);
return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
}
int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
int gpio_free(unsigned gpio)
{
return 0;
}
int gpio_direction_input(unsigned gpio)
{
s5p_gpio_direction_input(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio));
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
s5p_gpio_direction_output(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio), value);
return 0;
}
int gpio_get_value(unsigned gpio)
{
return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio));
}
int gpio_set_value(unsigned gpio, int value)
{
s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio), value);
return 0;
}
#endif /* HAVE_GENERIC_GPIO */
/*
* Add a delay here to give the lines time to settle
@ -439,49 +359,8 @@ int gpio_read_mvl3(unsigned gpio)
return value;
}
int gpio_decode_number(unsigned gpio_list[], int count)
{
int result = 0;
int multiplier = 1;
int gpio, i, value;
enum mvl3 mvl3;
for (i = 0; i < count; i++) {
gpio = gpio_list[i];
mvl3 = gpio_read_mvl3(gpio);
if (mvl3 == LOGIC_1)
value = 2;
else if (mvl3 == LOGIC_0)
value = 1;
else if (mvl3 == LOGIC_Z)
value = 0;
else
return -1;
result += value * multiplier;
multiplier *= 3;
}
return result;
}
#endif /* __BOOT_BLOCK__ */
static const char *get_cfg_name(int cfg)
{
static char name[8];
if (cfg == EXYNOS_GPIO_INPUT)
return "input";
else if (cfg == EXYNOS_GPIO_OUTPUT)
return "output";
printk(BIOS_INFO, "func %d", cfg);
// sprintf(name, "func %d", cfg);
return name;
}
/*
* Display Exynos GPIO information
*/
@ -492,7 +371,14 @@ void gpio_info(void)
for (gpio = 0; gpio < GPIO_MAX_PORT; gpio++) {
int cfg = gpio_get_cfg(gpio);
printk(BIOS_INFO, "GPIO_%-3d: %s", gpio, get_cfg_name(cfg));
printk(BIOS_INFO, "GPIO_%-3d: ", gpio);
if (cfg == EXYNOS_GPIO_INPUT)
printk(BIOS_INFO, "input");
else if (cfg == EXYNOS_GPIO_OUTPUT)
printk(BIOS_INFO, "output");
else
printk(BIOS_INFO, "func %d", cfg);
if (cfg == EXYNOS_GPIO_INPUT || cfg == EXYNOS_GPIO_OUTPUT)
printk(BIOS_INFO, ", value = %d", gpio_get_value(gpio));
printk(BIOS_INFO, "\n");

240
src/cpu/samsung/exynos5250/gpio.h
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (C) 2010 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,14 +14,11 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef EXYNOS5250_GPIO_H_
#define EXYNOS5250_GPIO_H_
#include <cpu/samsung/exynos5250/cpu.h> /* FIXME: for S5PC110_GPIO_BASE */
#ifndef CPU_SAMSUNG_EXYNOS5250_GPIO_H
#define CPU_SAMSUNG_EXYNOS5250_GPIO_H
struct s5p_gpio_bank {
unsigned int con;
@ -33,99 +30,6 @@ struct s5p_gpio_bank {
unsigned char res1[8];
};
struct s5pc100_gpio {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank b;
struct s5p_gpio_bank c;
struct s5p_gpio_bank d;
struct s5p_gpio_bank e0;
struct s5p_gpio_bank e1;
struct s5p_gpio_bank f0;
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
struct s5p_gpio_bank g0;
struct s5p_gpio_bank g1;
struct s5p_gpio_bank g2;
struct s5p_gpio_bank g3;
struct s5p_gpio_bank i;
struct s5p_gpio_bank j0;
struct s5p_gpio_bank j1;
struct s5p_gpio_bank j2;
struct s5p_gpio_bank j3;
struct s5p_gpio_bank j4;
struct s5p_gpio_bank k0;
struct s5p_gpio_bank k1;
struct s5p_gpio_bank k2;
struct s5p_gpio_bank k3;
struct s5p_gpio_bank l0;
struct s5p_gpio_bank l1;
struct s5p_gpio_bank l2;
struct s5p_gpio_bank l3;
struct s5p_gpio_bank l4;
struct s5p_gpio_bank h0;
struct s5p_gpio_bank h1;
struct s5p_gpio_bank h2;
struct s5p_gpio_bank h3;
};
struct s5pc110_gpio {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank b;
struct s5p_gpio_bank c0;
struct s5p_gpio_bank c1;
struct s5p_gpio_bank d0;
struct s5p_gpio_bank d1;
struct s5p_gpio_bank e0;
struct s5p_gpio_bank e1;
struct s5p_gpio_bank f0;
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
struct s5p_gpio_bank g0;
struct s5p_gpio_bank g1;
struct s5p_gpio_bank g2;
struct s5p_gpio_bank g3;
struct s5p_gpio_bank i;
struct s5p_gpio_bank j0;
struct s5p_gpio_bank j1;
struct s5p_gpio_bank j2;
struct s5p_gpio_bank j3;
struct s5p_gpio_bank j4;
struct s5p_gpio_bank mp0_1;
struct s5p_gpio_bank mp0_2;
struct s5p_gpio_bank mp0_3;
struct s5p_gpio_bank mp0_4;
struct s5p_gpio_bank mp0_5;
struct s5p_gpio_bank mp0_6;
struct s5p_gpio_bank mp0_7;
struct s5p_gpio_bank mp1_0;
struct s5p_gpio_bank mp1_1;
struct s5p_gpio_bank mp1_2;
struct s5p_gpio_bank mp1_3;
struct s5p_gpio_bank mp1_4;
struct s5p_gpio_bank mp1_5;
struct s5p_gpio_bank mp1_6;
struct s5p_gpio_bank mp1_7;
struct s5p_gpio_bank mp1_8;
struct s5p_gpio_bank mp2_0;
struct s5p_gpio_bank mp2_1;
struct s5p_gpio_bank mp2_2;
struct s5p_gpio_bank mp2_3;
struct s5p_gpio_bank mp2_4;
struct s5p_gpio_bank mp2_5;
struct s5p_gpio_bank mp2_6;
struct s5p_gpio_bank mp2_7;
struct s5p_gpio_bank mp2_8;
struct s5p_gpio_bank res1[48];
struct s5p_gpio_bank h0;
struct s5p_gpio_bank h1;
struct s5p_gpio_bank h2;
struct s5p_gpio_bank h3;
};
/* functions */
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
@ -139,16 +43,6 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
static inline unsigned int s5p_gpio_base(int nr)
{
return S5PC110_GPIO_BASE;
}
#define s5pc110_gpio_get_nr(bank, pin) \
((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
/* Pin configurations */
#define GPIO_INPUT 0x0
#define GPIO_OUTPUT 0x1
@ -685,34 +579,8 @@ void gpio_set_drv(int gpio, int mode);
*/
void gpio_set_rate(int gpio, int mode);
/* FIXME(dhendrix) use generic arch/gpio.h API instead */
//int gpio_direction_input(unsigned gpio);
//int gpio_direction_output(unsigned gpio, int value);
/**
* Decode a list of GPIOs into an integer.
*
* TODO(sjg@chromium.org): This could perhaps become a generic function?
*
* Each GPIO pin can be put into three states using external resistors:
* - pulled up
* - pulled down
* - not connected
*
* Read each GPIO in turn to produce an integer value. The first GPIO
* produces a number 1 * (0 to 2), the second produces 3 * (0 to 2), etc.
* In this way, each GPIO increases the number of possible states by a
* factor of 3.
*
* @param gpio_list List of GPIO numbers to decode
* @param count Number of GPIOs in list
* @return -1 if the value cannot be determined, or any GPIO number is
* invalid. Otherwise returns the calculated value
*/
int gpio_decode_number(unsigned gpio_list[], int count);
/*
* similar to gpio_decode_number, but reads only a single GPIO
* reads only a single GPIO
*
* @param gpio GPIO to read
* @return -1 if the value cannot be determined. Otherwise returns
@ -720,6 +588,94 @@ int gpio_decode_number(unsigned gpio_list[], int count);
*/
int gpio_read_mvl3(unsigned gpio);
///////////////////////////////
/*
* Generic GPIO API for U-Boot
*
* GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
* by the SOC/architecture.
*
* Each GPIO can be an input or output. If an input then its value can
* be read as 0 or 1. If an output then its value can be set to 0 or 1.
* If you try to write an input then the value is undefined. If you try
* to read an output, barring something very unusual, you will get
* back the value of the output that you previously set.
*
* In some cases the operation may fail, for example if the GPIO number
* is out of range, or the GPIO is not available because its pin is
* being used by another function. In that case, functions may return
* an error value of -1.
*/
/**
* Make a GPIO an input.
*
* @param gpio GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_direction_input(unsigned gpio);
/**
* Make a GPIO an output, and set its value.
*
* @param gpio GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_direction_output(unsigned gpio, int value);
/**
* Get a GPIO's value. This will work whether the GPIO is an input
* or an output.
*
* @param gpio GPIO number
* @return 0 if low, 1 if high, -1 on error
*/
int gpio_get_value(unsigned gpio);
/**
* Set an output GPIO's value. The GPIO must already be an output or
* this function may have no effect.
*
* @param gpio GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_set_value(unsigned gpio, int value);
///////////////////////////////
void gpio_info(void);
enum gpio_types {
GPIO_IN,
GPIO_OUT,
GPIO_ALT, /* catch-all for alternate functions */
};
/*
* Many-value logic (3 states). This can be used for inputs whereby presence
* of external pull-up or pull-down resistors can be added to overcome internal
* pull-ups/pull-downs and force a single value.
*
* Thus, external pull resistors can force a 0 or 1 and if the value changes
* along with internal pull-up/down enable then the input is floating.
*
* Vpd | Vpu | MVL
* -----------------
* 0 | 0 | 0
* -----------------
* 0 | 1 | Z <-- floating input will follow internal pull up/down
* -----------------
* 1 | 1 | 1
*/
enum mvl3 {
LOGIC_0,
LOGIC_1,
LOGIC_Z, /* high impedence / tri-stated / floating */
};
#endif /* EXYNOS5250_GPIO_H_ */

29
src/cpu/samsung/exynos5250/i2c.c
View File

@ -1,14 +1,12 @@
/*
* This file is part of the coreboot project.
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -17,22 +15,16 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This code should work for both the S3C2400 and the S3C2410
* as they seem to have the same I2C controller inside.
* The different address mapping is handled by the s3c24xx.h files below.
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/i2c.h>
#include "cpu/samsung/exynos5250/clk.h"
#include "cpu/samsung/exynos5250/i2c.h"
#include "cpu/samsung/exynos5250/pinmux.h"
#include "clk.h"
#include "i2c.h"
#include "pinmux.h"
#define I2C_WRITE 0
#define I2C_READ 1
@ -61,7 +53,6 @@ enum {
};
static struct s3c24x0_i2c_bus i2c_buses[] = {
/* FIXME: exynos5250-specific? */
{
.bus_num = 0,
.regs = (struct s3c24x0_i2c *)0x12c60000,

24
src/cpu/samsung/exynos5250/i2c.h
View File

@ -1,13 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -16,15 +14,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _S3C24X0_I2C_H
#define _S3C24X0_I2C_H
#ifndef CPU_SAMSUNG_EXYNOS5250_I2C_H
#define CPU_SAMSUNG_EXYNOS5250_I2C_H
/* FIXME: gross hack */
#include "cpu/samsung/exynos5250/periph.h"
#include "periph.h"
struct s3c24x0_i2c {
u32 iiccon;
@ -42,4 +38,4 @@ struct s3c24x0_i2c_bus {
void i2c_init(unsigned bus, int speed, int slaveadd);
#endif /* _S3C24X0_I2C_H */
#endif /* CPU_SAMSUNG_EXYNOS5250_I2C_H */

26
src/cpu/samsung/exynos5250/i2s-regs.h
View File

@ -1,16 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
* R. Chandrasekar <rcsekar@samsung.com>
*
* Taken from the kernel code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -19,12 +14,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __I2S_REGS_H__
#define __I2S_REGS_H__
/* Taken from the kernel code */
#ifndef CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H
#define CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H
#define I2SCON 0x0
#define I2SMOD 0x4
@ -143,4 +139,4 @@
#define I2SSIZE_TRNMSK (0xffff)
#define I2SSIZE_SHIFT (16)
#endif /* __I2S_REGS_H__ */
#endif /* CPU_SAMSUNG_EXYNOS5250_I2S_REGS_H */

133
src/cpu/samsung/exynos5250/lowlevel_init_c.c
View File

@ -1,133 +0,0 @@
/*
* Lowlevel setup for SMDK5250 board based on S5PC520
*
* Copyright (C) 2012 Samsung Electronics
* Copyright (c) 2012 The Chromium OS Authors.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* FIXME: This file is essentially the "bootblock" leftover from U-Boot. For
* now it serves as a reference until all the resume-related stuff is added
* to the appropriate bootblock/romstage/ramstage files in coreboot.
*/
#include <common.h>
#include <config.h>
#include <cpu/samsung/exynos5-common/exynos5-common.h>
#include <cpu/samsung/exynos5-common/spl.h>
#include <cpu/samsung/exynos5250/clock_init.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/dmc.h>
#include <cpu/samsung/exynos5250/pinmux.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/tzpc.h>
#include "setup.h"
#include <console/console.h>
void do_barriers(void); /* FIXME: make gcc shut up about "no previous prototype" */
void do_barriers(void)
{
/*
* The reason we don't write out the instructions dsb/isb/sev:
* While ARM Cortex-A8 supports ARM v7 instruction set (-march=armv7a),
* we compile with -march=armv5 to allow more compilers to work.
* For U-Boot code this has no performance impact.
*/
__asm__ __volatile__(
#if defined(__thumb__)
".hword 0xF3BF, 0x8F4F\n" /* dsb; darn -march=armv5 */
".hword 0xF3BF, 0x8F6F\n" /* isb; darn -march=armv5 */
".hword 0xBF40\n" /* sev; darn -march=armv5 */
#else
".word 0xF57FF04F\n" /* dsb; darn -march=armv5 */
".word 0xF57FF06F\n" /* isb; darn -march=armv5 */
".word 0xE320F004\n" /* sev; darn -march=armv5 */
#endif
);
}
/* These are the things we can do during low-level init */
enum {
DO_WAKEUP = 1 << 0,
DO_UART = 1 << 1,
DO_CLOCKS = 1 << 2,
DO_POWER = 1 << 3,
};
int lowlevel_init_subsystems(void)
{
// uint32_t reset_status;
int actions = 0;
// do_barriers();
/* Setup cpu info which is needed to select correct register offsets */
cpu_info_init();
#if 0
reset_status = power_read_reset_status();
switch (reset_status) {
case S5P_CHECK_SLEEP:
actions = DO_CLOCKS | DO_WAKEUP;
break;
case S5P_CHECK_DIDLE:
case S5P_CHECK_LPA:
actions = DO_WAKEUP;
default:
/* This is a normal boot (not a wake from sleep) */
actions = DO_UART | DO_CLOCKS | DO_POWER;
}
#endif
actions = DO_UART | DO_CLOCKS | DO_POWER;
if (actions & DO_POWER)
power_init();
if (actions & DO_CLOCKS)
system_clock_init();
if (actions & DO_UART) {
/* Set up serial UART so we can printf() */
/* FIXME(dhendrix): add a function for mapping
CONFIG_CONSOLE_SERIAL_UART_ADDRESS to PERIPH_ID_UARTn */
// exynos_pinmux_config(EXYNOS_UART, PINMUX_FLAG_NONE);
exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
console_init();
while (1) {
console_tx_byte('C');
}
}
init_timer(); /* FIXME(dhendrix): was timer_init() */
#if 0
if (actions & DO_CLOCKS) {
mem_ctrl_init();
tzpc_init();
}
#endif
// return actions & DO_WAKEUP;
return 0;
}

20
src/cpu/samsung/exynos5250/mct.c
View File

@ -1,28 +1,24 @@
/*
* Copyright 2013 Google Inc.
* This file is part of the coreboot project.
*
* See file CREDITS for list of people who contributed to this
* project.
* Copyright 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but without any warranty; without even the implied warranty of
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <stdint.h>
#include <arch/io.h>
#include "clk.h"
struct __attribute__((packed)) mct_regs

2
src/cpu/samsung/exynos5250/monotonic_timer.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

20
src/cpu/samsung/exynos5250/periph.h
View File

@ -1,10 +1,11 @@
/*
* (C) Copyright 2012 The Chromium Authors
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -13,13 +14,11 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS_PERIPH_H
#define __EXYNOS_PERIPH_H
#ifndef CPU_SAMSUNG_EXYNOS5250_PERIPH_H
#define CPU_SAMSUNG_EXYNOS5250_PERIPH_H
/*
* Peripherals requiring clock/pinmux configuration. List will
@ -38,7 +37,6 @@ enum periph_id {
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
/* TODO: make sequential again when FDT doesn't hardcode. */
PERIPH_ID_SROMC = 9,
PERIPH_ID_SPI0,
PERIPH_ID_SPI1,

37
src/cpu/samsung/exynos5250/pinmux.c
View File

@ -1,32 +1,27 @@
/*
* Copyright (c) 2012 Samsung Electronics.
* Abhilash Kesavan <a.kesavan@samsung.com>
* This file is part of the coreboot project.
*
* See file CREDITS for list of people who contributed to this
* project.
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
#include <arch/gpio.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/pinmux.h>
#include <cpu/samsung/exynos5250/sromc.h>
#include <console/console.h>
#include <assert.h>
#include "gpio.h"
#include "cpu.h"
#include "pinmux.h"
int exynos_pinmux_config(enum periph_id peripheral, int flags)
{
@ -88,16 +83,16 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags)
* TODO: Need to add defintions for GPC4 before
* enabling this.
*/
debug("SDMMC3 not supported yet");
printk(BIOS_DEBUG, "SDMMC3 not supported yet");
return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
printk(BIOS_DEBUG, "SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
assert(peripheral == PERIPH_ID_SDMMC0);
ASSERT(peripheral == PERIPH_ID_SDMMC0);
for (i = 0; i <= 3; i++) {
gpio_cfg_pin(start_ext + i, pin_ext);
gpio_set_pull(start_ext + i,
@ -295,7 +290,7 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags)
gpio_cfg_pin(GPIO_B00 + i, EXYNOS_GPIO_FUNC(0x02));
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
return -1;
}

22
src/cpu/samsung/exynos5250/pinmux.h
View File

@ -1,29 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS_PINMUX_H
#define __EXYNOS_PINMUX_H
#ifndef CPU_SAMSUNG_EXYNOS5250_PINMUX_H
#define CPU_SAMSUNG_EXYNOS5250_PINMUX_H
//#include <asm/arch/periph.h>
#include "periph.h"
enum {

29
src/cpu/samsung/exynos5250/power.c
View File

@ -1,15 +1,11 @@
/*
* Power setup code for EXYNOS5
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,18 +14,17 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
#include <arch/hlt.h>
/* Power setup code for EXYNOS5 */
#include <console/console.h>
#include <arch/io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/sysreg.h>
#include "cpu.h"
#include "power.h"
#include "sysreg.h"
static void ps_hold_setup(void)
{
@ -81,7 +76,7 @@ void power_enable_usb_phy(void)
/* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
phy_cfg = readl(&sysreg->usb20_phy_cfg);
if (phy_cfg & USB20_PHY_CFG_EN) {
debug("USB 2.0 HOST link already selected\n");
printk(BIOS_DEBUG, "USB 2.0 HOST link already selected\n");
} else {
phy_cfg |= USB20_PHY_CFG_EN;
writel(phy_cfg, &sysreg->usb20_phy_cfg);

35
src/cpu/samsung/exynos5250/power.h
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Register map for Exynos5 PMU
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,28 +14,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS5_POWER_H__
#define __EXYNOS5_POWER_H__
/* Register map for Exynos5 PMU */
/*
* Power control
*/
#define S5PC100_OTHERS 0xE0108200
#define S5PC100_RST_STAT 0xE0108300
#define S5PC100_SLEEP_WAKEUP (1 << 3)
#define S5PC100_WAKEUP_STAT 0xE0108304
#define S5PC100_INFORM0 0xE0108400
#define S5PC110_RST_STAT 0xE010A000
#define S5PC110_SLEEP_WAKEUP (1 << 3)
#define S5PC110_WAKEUP_STAT 0xE010C200
#define S5PC110_OTHERS 0xE010E000
#define S5PC110_USB_PHY_CON 0xE010E80C
#define S5PC110_INFORM0 0xE010F000
#ifndef CPU_SAMSUNG_EXYNOS5250_POWER_H
#define CPU_SAMSUNG_EXYNOS5250_POWER_H
/* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
void power_enable_hw_thermal_trip(void);

28
src/cpu/samsung/exynos5250/pwm.c
View File

@ -1,15 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Samsung Electronics
*
* Donghwa Lee <dh09.lee@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,16 +14,14 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
#include <arch/io.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/pwm.h>
#include "clk.h"
#include "cpu.h"
#include "periph.h"
#include "pwm.h"
int pwm_enable(int pwm_id)
{
@ -100,11 +94,9 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
*/
if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
return -1;
// return -ERANGE;
if (duty_ns > period_ns)
return -1;
// return -EINVAL;
frequency = NS_IN_SEC / period_ns;

22
src/cpu/samsung/exynos5250/pwm.h
View File

@ -1,12 +1,11 @@
/*
* Copyright (C) 2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
* Minkyu Kang <mk7.kang@samsung.com>
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (C) 2009 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -15,12 +14,11 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_ARM_ARCH_COMMON_PWM_H_
#define __ASM_ARM_ARCH_COMMON_PWM_H_
#ifndef CPU_SAMSUNG_EXYNOS5250_PWM_H
#define CPU_SAMSUNG_EXYNOS5250_PWM_H
#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
@ -42,7 +40,6 @@
#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
#define TCON4_AUTO_RELOAD (1 << 22)
#ifndef __ASSEMBLER__
struct s5p_timer {
unsigned int tcfg0;
unsigned int tcfg1;
@ -69,6 +66,5 @@ int pwm_check_enabled(int pwm_id);
void pwm_disable(int pwm_id);
int pwm_enable(int pwm_id);
int pwm_init(int pwm_id, int div, int invert);
#endif /* __ASSEMBLER__ */
#endif

18
src/cpu/samsung/exynos5250/reset.c
View File

@ -1,24 +1,20 @@
/*
* Copyright (c) 2010 Samsung Electronics.
* Minkyu Kang <mk7.kang@samsung.com>
* This file is part of the coreboot project.
*
* See file CREDITS for list of people who contributed to this
* project.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <reset.h>

431
src/cpu/samsung/exynos5250/sata.c
View File

@ -1,431 +0,0 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ahci.h>
#include <common.h>
#include <fdtdec.h>
#include <scsi.h>
#include <asm/arch-exynos5/sata.h>
#include <asm/arch/pinmux.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/types.h>
#define SATA_AHCI_AXI 0x122f0000
#define SATA_PHCTRL_APB 0x12170000
#define SATA_PHY_I2C_ABP 0x121d0000
#define EXYNOS5_SATA_PHY_CONTROL (0x10040000 + 0x724)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
void * const phy_ctrl = (void *)SATA_PHCTRL_APB;
void * const phy_i2c_base = (void *)SATA_PHY_I2C_ABP;
typedef unsigned char bool;
#define true 1
#define false 0
#define SATA_TIME_LIMIT 10000
#define SATA_PHY_I2C_SLAVE_ADDRS 0x70
#define SATA_RESET 0x4
#define RESET_CMN_RST_N (1 << 1)
#define LINK_RESET 0xF0000
#define SATA_MODE0 0x10
#define SATA_CTRL0 0x14
#define CTRL0_P0_PHY_CALIBRATED_SEL (1 << 9)
#define CTRL0_P0_PHY_CALIBRATED (1 << 8)
#define SATA_PHSATA_CTRLM 0xE0
#define PHCTRLM_REF_RATE (1 << 1)
#define PHCTRLM_HIGH_SPEED (1 << 0)
#define SATA_PHSATA_STATM 0xF0
#define PHSTATM_PLL_LOCKED (1 << 0)
/********************** I2C**************/
#define SATA_I2C_CON 0x00
#define SATA_I2C_STAT 0x04
#define SATA_I2C_ADDR 0x08
#define SATA_I2C_DS 0x0C
#define SATA_I2C_LC 0x10
/* I2CCON reg */
#define CON_ACKEN (1 << 7)
#define CON_CLK512 (1 << 6)
#define CON_CLK16 (~CON_CLK512)
#define CON_INTEN (1 << 5)
#define CON_INTPND (1 << 4)
#define CON_TXCLK_PS (0xF)
/* I2CSTAT reg */
#define STAT_MSTT (0x3 << 6)
#define STAT_BSYST (1 << 5)
#define STAT_RTEN (1 << 4)
#define STAT_LAST (1 << 0)
#define LC_FLTR_EN (1 << 2)
#define SATA_PHY_CON_RESET 0xF003F
#define SCLK_SATA_FREQ (66 * MHZ)
enum {
SATA_GENERATION1,
SATA_GENERATION2,
SATA_GENERATION3,
};
static bool sata_is_reg(void __iomem *base, u32 reg, u32 checkbit, u32 Status)
{
if ((__raw_readl(base + reg) & checkbit) == Status)
return true;
else
return false;
}
static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
u32 Status)
{
u32 time_limit_cnt = 0;
while (!sata_is_reg(base, reg, checkbit, Status)) {
if (time_limit_cnt == SATA_TIME_LIMIT) {
return false;
}
udelay(1000);
time_limit_cnt++;
}
return true;
}
static void sata_set_gen(u8 gen)
{
__raw_writel(gen, phy_ctrl + SATA_MODE0);
}
/* Address :I2C Address */
static void sata_i2c_write_addrs(u8 data)
{
__raw_writeb((data & 0xFE), phy_i2c_base + SATA_I2C_DS);
}
static void sata_i2c_write_data(u8 data)
{
__raw_writeb((data), phy_i2c_base + SATA_I2C_DS);
}
static void sata_i2c_start(void)
{
u32 val;
val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
val |= STAT_BSYST;
__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
}
static void sata_i2c_stop(void)
{
u32 val;
val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
val &= ~STAT_BSYST;
__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
}
static bool sata_i2c_get_int_status(void)
{
if ((__raw_readl(phy_i2c_base + SATA_I2C_CON)) & CON_INTPND)
return true;
else
return false;
}
static bool sata_i2c_is_tx_ack(void)
{
if ((__raw_readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_LAST)
return false;
else
return true;
}
static bool sata_i2c_is_bus_ready(void)
{
if ((__raw_readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_BSYST)
return false;
else
return true;
}
static bool sata_i2c_wait_for_busready(u32 time_out)
{
while (--time_out) {
if (sata_i2c_is_bus_ready())
return true;
udelay(100);
}
return false;
}
static bool sata_i2c_wait_for_tx_ack(u32 time_out)
{
while (--time_out) {
if (sata_i2c_get_int_status()) {
if (sata_i2c_is_tx_ack())
return true;
}
udelay(100);
}
return false;
}
static void sata_i2c_clear_int_status(void)
{
u32 val;
val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
val &= ~CON_INTPND;
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
}
static void sata_i2c_set_ack_gen(bool enable)
{
u32 val;
if (enable) {
val = (__raw_readl(phy_i2c_base + SATA_I2C_CON)) | CON_ACKEN;
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
} else {
val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
val &= ~CON_ACKEN;
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
}
}
static void sata_i2c_set_master_tx(void)
{
u32 val;
/* Disable I2C */
val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
val &= ~STAT_RTEN;
__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
/* Clear Mode */
val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
val &= ~STAT_MSTT;
__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
sata_i2c_clear_int_status();
/* interrupt disable */
val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
val &= ~CON_INTEN;
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
/* Master, Send mode */
val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
val |= STAT_MSTT;
__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
/* interrupt enable */
val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
val |= CON_INTEN;
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
/* Enable I2C */
val = __raw_readl(phy_i2c_base + SATA_I2C_STAT);
val |= STAT_RTEN;
__raw_writel(val, phy_i2c_base + SATA_I2C_STAT);
}
static void sata_i2c_init(void)
{
u32 val;
val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
val &= CON_CLK16;
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
val &= ~(CON_TXCLK_PS);
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
val = __raw_readl(phy_i2c_base + SATA_I2C_CON);
val |= (2 & CON_TXCLK_PS);
__raw_writel(val, phy_i2c_base + SATA_I2C_CON);
val = __raw_readl(phy_i2c_base + SATA_I2C_LC);
val &= ~(LC_FLTR_EN);
__raw_writel(val, phy_i2c_base + SATA_I2C_LC);
sata_i2c_set_ack_gen(false);
}
static bool sata_i2c_send(u8 slave_addrs, u8 addrs, u8 ucData)
{
s32 ret = 0;
if (!sata_i2c_wait_for_busready(SATA_TIME_LIMIT))
return false;
sata_i2c_init();
sata_i2c_set_master_tx();
__raw_writel(SATA_PHY_CON_RESET, phy_ctrl + SATA_RESET);
sata_i2c_write_addrs(slave_addrs);
sata_i2c_start();
if (!sata_i2c_wait_for_tx_ack(SATA_TIME_LIMIT)) {
ret = false;
goto STOP;
}
sata_i2c_write_data(addrs);
sata_i2c_clear_int_status();
if (!sata_i2c_wait_for_tx_ack(SATA_TIME_LIMIT)) {
ret = false;
goto STOP;
}
sata_i2c_write_data(ucData);
sata_i2c_clear_int_status();
if (!sata_i2c_wait_for_tx_ack(SATA_TIME_LIMIT)) {
ret = false;
goto STOP;
}
ret = true;
STOP:
sata_i2c_stop();
sata_i2c_clear_int_status();
sata_i2c_wait_for_busready(SATA_TIME_LIMIT);
return ret;
}
static bool ahci_phy_init(void __iomem *mmio)
{
u8 uCount, i = 0;
/* 0x3A for 40bit I/F */
u8 reg_addrs[] = {0x22, 0x21, 0x3A};
/* 0x0B for 40bit I/F */
u8 default_setting_value[] = {0x30, 0x4f, 0x0B};
uCount = sizeof(reg_addrs)/sizeof(u8);
while (i < uCount) {
if (!sata_i2c_send(SATA_PHY_I2C_SLAVE_ADDRS, reg_addrs[i],
default_setting_value[i]))
return false;
i++;
}
return true;
}
static int exynos5_ahci_init(void __iomem *mmio)
{
int val, ret;
__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, EXYNOS5_SATA_PHY_CONTROL);
val = 0;
__raw_writel(val, phy_ctrl + SATA_RESET);
val = __raw_readl(phy_ctrl + SATA_RESET);
val |= 0x3D;
__raw_writel(val, phy_ctrl + SATA_RESET);
val = __raw_readl(phy_ctrl + SATA_RESET);
val |= LINK_RESET;
__raw_writel(val, phy_ctrl + SATA_RESET);
val = __raw_readl(phy_ctrl + SATA_RESET);
val |= RESET_CMN_RST_N;
__raw_writel(val, phy_ctrl + SATA_RESET);
val = __raw_readl(phy_ctrl + SATA_PHSATA_CTRLM);
val &= ~PHCTRLM_REF_RATE;
__raw_writel(val, phy_ctrl + SATA_PHSATA_CTRLM);
/* High speed enable for Gen3 */
val = __raw_readl(phy_ctrl + SATA_PHSATA_CTRLM);
val |= PHCTRLM_HIGH_SPEED;
__raw_writel(val, phy_ctrl + SATA_PHSATA_CTRLM);
/* Port0 is available */
__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
ret = ahci_phy_init(mmio);
val = __raw_readl(phy_ctrl + SATA_CTRL0);
val |= CTRL0_P0_PHY_CALIBRATED_SEL|CTRL0_P0_PHY_CALIBRATED;
__raw_writel(val, phy_ctrl + SATA_CTRL0);
sata_set_gen(SATA_GENERATION3);
/* release cmu reset */
val = __raw_readl(phy_ctrl + SATA_RESET);
val &= ~RESET_CMN_RST_N;
__raw_writel(val, phy_ctrl + SATA_RESET);
val = __raw_readl(phy_ctrl + SATA_RESET);
val |= RESET_CMN_RST_N;
__raw_writel(val, phy_ctrl + SATA_RESET);
if (wait_for_reg_status(phy_ctrl, SATA_PHSATA_STATM,
PHSTATM_PLL_LOCKED, 1)) {
return ret;
}
return 0;
}
static int exynos5_sata_enable_power(const void *blob)
{
int node;
struct fdt_gpio_state gpio;
node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_SATA);
if (node >= 0 &&
fdtdec_decode_gpio(blob, node, "enable-gpios", &gpio) == 0) {
gpio_cfg_pin(gpio.gpio, EXYNOS_GPIO_OUTPUT);
gpio_set_value(gpio.gpio, 1);
return 0;
}
return -ENODEV;
}
static void exynos5_enable_clock_gates(void)
{
/* Turn on all SATA clock gates & DMA gates. */
const unsigned cmu_toppart = 0x10020000;
const unsigned addr = cmu_toppart + 0x944;
const unsigned sata_clocks = (1 << 25) | (1 << 24) | (1 << 6);
const unsigned dma_clocks = (2 << 1) | (1 << 1);
const unsigned clk_gate_ip_fsys = readl(addr);
writel(clk_gate_ip_fsys | sata_clocks | dma_clocks, addr);
}
int exynos5_sata_init(const void *blob)
{
if (exynos5_sata_enable_power(blob) == 0) {
exynos5_enable_clock_gates();
if (exynos5_ahci_init((void *)SATA_AHCI_AXI)) {
ahci_init(SATA_AHCI_AXI);
scsi_scan(1);
return 0;
}
}
return -ENODEV;
}

27
src/cpu/samsung/exynos5250/sata.h
View File

@ -1,27 +0,0 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __EXYNOS5_SATA_H
#define __EXYNOS5_SATA_H
int exynos5_sata_init(const void *blob);
#endif

24
src/cpu/samsung/exynos5250/setup.h
View File

@ -1,15 +1,11 @@
/*
* Machine Specific Values for SMDK5250 board based on Exynos5
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,12 +14,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _SMDK5250_SETUP_H
#define _SMDK5250_SETUP_H
/* Machine Specific Values for SMDK5250 board based on Exynos5 */
#ifndef CPU_SAMSUNG_EXYNOS5250_SETUP_H
#define CPU_SAMSUNG_EXYNOS5250_SETUP_H
struct exynos5_dmc;
enum ddr_mode;
@ -687,8 +684,6 @@ enum {
};
/* Functions common between LPDDR2 and DDR3 */
/* FIXME(dhendrix): conflicts with arch system.h version of sdelay()... */
//void sdelay(unsigned long);
/* CPU info initialization code */
void cpu_info_init(void);
@ -708,7 +703,6 @@ void mem_ctrl_init(void);
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
int mem_reset);
void tzpc_init(void);
/*
* Configure ZQ I/O interface
*

31
src/cpu/samsung/exynos5250/spi.c
View File

@ -1,14 +1,12 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Samsung Electronics
* Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
* Copyright 2013 Google Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -17,18 +15,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdlib.h>
#include <common.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <arch/io.h>
#include <stdlib.h>
#include <assert.h>
#include "gpio.h"
#include "clk.h"
#include "spi.h"
#define OM_STAT (0x1f << 1)
@ -49,7 +44,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
// TODO In currrent implementation, every read/write must be aligned to
// 4 bytes, otherwise you may get timeout or other unexpected results.
assert(todo % 4 == 0);
ASSERT(todo % 4 == 0);
out_bytes = in_bytes = todo;
setbits_le32(&regs->ch_cfg, SPI_CH_RST);

23
src/cpu/samsung/exynos5250/spi.h
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2012 SAMSUNG Electronics
* Padmavathi Venna <padma.v@samsung.com>
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,17 +14,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
#ifndef CPU_SAMSUNG_EXYNOS5250_SPI_H
#define CPU_SAMSUNG_EXYNOS5250_SPI_H
// This driver serves as a CBFS media source.
/* This driver serves as a CBFS media source. */
#include <cbfs.h>
#ifndef __ASSEMBLER__
/* SPI peripheral register map; padded to 64KB */
struct exynos_spi {
unsigned int ch_cfg; /* 0x00 */
@ -93,11 +91,8 @@ int exynos_spi_open(struct exynos_spi *regs);
int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off);
int exynos_spi_close(struct exynos_spi *regs);
/* Serve as CBFS Media */
/* Serve as CBFS media source */
int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
void *buffer_address,
size_t buffer_size);
#endif /* __ASSEMBLER__ */
#endif

49
src/cpu/samsung/exynos5250/sromc.c
View File

@ -1,49 +0,0 @@
/*
* Copyright (C) 2010 Samsung Electronics
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sromc.h>
/*
* s5p_config_sromc() - select the proper SROMC Bank and configure the
* band width control and bank control registers
* srom_bank - SROM
* srom_bw_conf - SMC Band witdh reg configuration value
* srom_bc_conf - SMC Bank Control reg configuration value
*/
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
{
u32 tmp;
struct s5p_sromc *srom =
samsung_get_base_sromc();
/* Configure SMC_BW register to handle proper SROMC bank */
tmp = srom->bw;
tmp &= ~(0xF << (srom_bank * 4));
tmp |= srom_bw_conf;
srom->bw = tmp;
/* Configure SMC_BC register */
srom->bc[srom_bank] = srom_bc_conf;
}

69
src/cpu/samsung/exynos5250/sromc.h
View File

@ -1,69 +0,0 @@
/*
* (C) Copyright 2010 Samsung Electronics
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: This file contains the register description for SROMC
*
*/
#ifndef __ASM_ARCH_COMMON_SROMC_H_
#define __ASM_ARCH_COMMON_SROMC_H_
#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
/* 1-> Byte base address*/
#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
#ifndef __ASSEMBLER__
struct s5p_sromc {
unsigned int bw;
unsigned int bc[4];
};
#endif /* __ASSEMBLER__ */
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
enum {
FDT_SROM_PMC,
FDT_SROM_TACP,
FDT_SROM_TAH,
FDT_SROM_TCOH,
FDT_SROM_TACC,
FDT_SROM_TCOS,
FDT_SROM_TACS,
FDT_SROM_TIMING_COUNT,
};
struct fdt_sromc {
u8 bank; /* srom bank number */
u8 width; /* bus width in bytes */
unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
};
#endif /* __ASM_ARCH_COMMON_SROMC_H_ */

21
src/cpu/samsung/exynos5250/sysreg.h
View File

@ -1,11 +1,11 @@
/*
* (C) Copyright 2012 Samsung Electronics
* Register map for Exynos5 sysreg
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -14,12 +14,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS5_SYSREG_H__
#define __EXYNOS5_SYSREG_H__
/* Register map for Exynos5 sysreg */
#ifndef CPU_SAMSUNG_EXYNOS5250_SYSREG_H
#define CPU_SAMSUNG_EXYNOS5250_SYSREG_H
/* sysreg map */
struct exynos5_sysreg {

84
src/cpu/samsung/exynos5250/timer.c
View File

@ -1,16 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
* Inki Dae <inki.dae@samsung.com>
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -19,22 +14,18 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
#include <console/console.h>
#include <arch/io.h>
#include <timer.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/pwm.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/exynos5-common.h>
#include <delay.h>
#include "timer.h"
#include "pwm.h"
#include "clk.h"
#include "cpu.h"
//#include <pwm.h>
//DECLARE_GLOBAL_DATA_PTR;
static unsigned long long timer_reset_value;
static unsigned long lastinc;
@ -59,7 +50,7 @@ static unsigned long timer_get_us_down(void)
return readl(&timer->tcnto4);
}
int init_timer(void)
void init_timer(void)
{
/* Timer may have been enabled in SPL */
if (!pwm_check_enabled(4)) {
@ -69,15 +60,11 @@ int init_timer(void)
pwm_enable(4);
/* Use this as the current monotonic time in us */
//gd->timer_reset_value = 0;
timer_reset_value = 0;
/* Use this as the last timer value we saw */
//gd->lastinc = timer_get_us_down();
lastinc = timer_get_us_down();
}
return 0;
}
/*
@ -92,13 +79,6 @@ unsigned long get_timer(unsigned long base)
* The timer may have wrapped around, but it makes no difference to
* our arithmetic here.
*/
#if 0
gd->timer_reset_value += gd->lastinc - now;
gd->lastinc = now;
/* Divide by 1000 to convert from us to ms */
return gd->timer_reset_value / 1000 - base;
#endif
timer_reset_value += lastinc - now;
lastinc = now;
@ -106,20 +86,8 @@ unsigned long get_timer(unsigned long base)
return timer_reset_value / 1000 - base;
}
unsigned long timer_get_us(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long now_downward_us = readl(&timer->tcnto4);
/*
* Note that this timer counts downward. The pre-SPL process (BL1)
* takes about 100ms, so add this in here.
*/
return CONFIG_SPL_TIME_US - now_downward_us;
}
/* delay x useconds */
void udelay(unsigned long usec)
void udelay(unsigned usec)
{
struct mono_time current, end;
@ -128,7 +96,7 @@ void udelay(unsigned long usec)
mono_time_add_usecs(&end, usec);
if (mono_time_after(&current, &end)) {
printk(BIOS_EMERG, "udelay: 0x%08lx is impossibly large\n",
printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n",
usec);
/* There's not much we can do if usec is too big. Use a long,
* paranoid delay value and hope for the best... */
@ -140,25 +108,3 @@ void udelay(unsigned long usec)
timer_monotonic_get(&current);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
unsigned long get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
unsigned long timer_get_boot_us(void)
{
return timer_get_us();
}

32
src/cpu/samsung/exynos5250/soc.c → src/cpu/samsung/exynos5250/timer.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -17,31 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/periph.h>
#ifndef CPU_SAMSUNG_EXYNOS5250_TIMER_H
#define CPU_SAMSUNG_EXYNOS5250_TIMER_H
#include <cpu/samsung/exynos5250/uart.h>
unsigned long get_timer(unsigned long base);
enum periph_id exynos5_get_periph_id(unsigned base_addr)
{
enum periph_id id = PERIPH_ID_NONE;
switch (base_addr) {
case EXYNOS5_UART0_BASE:
id = PERIPH_ID_UART0;
break;
case EXYNOS5_UART1_BASE:
id = PERIPH_ID_UART1;
break;
case EXYNOS5_UART2_BASE:
id = PERIPH_ID_UART2;
break;
case EXYNOS5_UART3_BASE:
id = PERIPH_ID_UART3;
break;
default:
break;
}
return id;
}
#endif

50
src/cpu/samsung/exynos5250/exynos-tmu.c → src/cpu/samsung/exynos5250/tmu.c
View File

@ -1,28 +1,29 @@
/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Akshay Saraswat <Akshay.s@samsung.com>
* Copyright (c) 2013 Google Inc.
* This file is part of the coreboot project.
*
* EXYNOS - Thermal Management Unit
*
* This file was originally imported from Das U-Boot and then re-factored
* for coreboot.
* Copyright (C) 2012 Samsung Electronics
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/exynos-tmu.h>
/* EXYNOS - Thermal Management Unit */
#include <console/console.h>
#include <arch/io.h>
#include "power.h"
#include "tmu.h"
#define TRIMINFO_RELOAD 1
#define CORE_EN 1
@ -47,6 +48,25 @@
INTCLEAR_RISE2 | INTCLEAR_FALL0 | \
INTCLEAR_FALL1 | INTCLEAR_FALL2)
struct tmu_info exynos5250_tmu_info = {
.tmu_base = 0x10060000,
.tmu_mux = 6,
.data = {
.ts = {
.min_val = 25,
.max_val = 125,
.start_warning = 95,
.start_tripping = 105,
.hardware_tripping = 110,
},
.efuse_min_value = 40,
.efuse_value = 55,
.efuse_max_value = 100,
.slope = 0x10008802,
},
.dc_value = 25,
};
/*
* After reading temperature code from register, compensating
* its value and calculating celsius temperatue,

30
src/cpu/samsung/exynos5250/exynos-tmu.h → src/cpu/samsung/exynos5250/tmu.h
View File

@ -1,24 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Akshay Saraswat <Akshay.s@samsung.com>
*
* EXYNOS - Thermal Management Unit
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS_TMU_H
#define __EXYNOS_TMU_H
/* EXYNOS - Thermal Management Unit */
#ifndef CPU_SAMSUNG_EXYNOS5250_TMU_H
#define CPU_SAMSUNG_EXYNOS5250_TMU_H
struct tmu_reg {
unsigned triminfo;
@ -129,4 +131,4 @@ enum tmu_status_t tmu_monitor(struct tmu_info *info, int *temp);
*/
int tmu_init(struct tmu_info *info);
#endif /* EXYNOS_TMU_H */
#endif /* CPU_SAMSUNG_EXYNOS5250_TMU_H */

52
src/cpu/samsung/exynos5250/tzpc.h
View File

@ -1,52 +0,0 @@
/*
* (C) Copyright 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __TZPC_H_
#define __TZPC_H_
#ifndef __ASSEMBLER__
struct exynos5_tzpc {
unsigned int r0size;
char res1[0x7FC];
unsigned int decprot0stat;
unsigned int decprot0set;
unsigned int decprot0clr;
unsigned int decprot1stat;
unsigned int decprot1set;
unsigned int decprot1clr;
unsigned int decprot2stat;
unsigned int decprot2set;
unsigned int decprot2clr;
unsigned int decprot3stat;
unsigned int decprot3set;
unsigned int decprot3clr;
char res2[0x7B0];
unsigned int periphid0;
unsigned int periphid1;
unsigned int periphid2;
unsigned int periphid3;
unsigned int pcellid0;
unsigned int pcellid1;
unsigned int pcellid2;
unsigned int pcellid3;
};
#endif
#endif

57
src/cpu/samsung/exynos5250/tzpc_init.c
View File

@ -1,57 +0,0 @@
/*
* Lowlevel setup for SMDK5250 board based on S5PC520
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <cpu/samsung/exynos5250/cpu.h>
#include <asm/arch/dmc.h>
#include <asm/arch/tzpc.h>
#include"setup.h"
/* Setting TZPC[TrustZone Protection Controller] */
void tzpc_init(void)
{
struct exynos5_tzpc *tzpc;
unsigned int addr;
for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
tzpc = (struct exynos5_tzpc *)addr;
if (addr == TZPC0_BASE)
writel(R0SIZE, &tzpc->r0size);
writel(DECPROTXSET, &tzpc->decprot0set);
writel(DECPROTXSET, &tzpc->decprot1set);
if (addr == TZPC9_BASE) {
/* TODO: Add comment here describing the numerical values
* used below.
*/
writel(0xf0, &tzpc->decprot2set);
writel(0x50, &tzpc->decprot3set);
} else {
writel(DECPROTXSET, &tzpc->decprot2set);
writel(DECPROTXSET, &tzpc->decprot3set);
}
}
}

58
src/cpu/samsung/exynos5250/uart.c
View File

@ -1,14 +1,11 @@
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Heungjun Kim <riverful.kim@samsung.com>
* This file is part of the coreboot project.
*
* based on drivers/serial/s3c64xx.c
* Copyright (C) 2009 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -17,19 +14,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <console/console.h> /* for __console definition */
#include <uart.h>
#include <arch/io.h>
#include <console/console.h> /* for __console definition */
#include <cpu/samsung/exynos5250/exynos5-common.h>
#include <cpu/samsung/exynos5250/uart.h>
#include <cpu/samsung/exynos5250/clk.h>
#include "uart.h"
#include "clk.h"
#include "cpu.h"
#define RX_FIFO_COUNT_MASK 0xff
#define RX_FIFO_FULL_MASK (1 << 8)
@ -38,24 +31,6 @@
/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a
base_port argument. However console_driver functions do not. */
static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
#if 0
/* Information about a serial port */
struct fdt_serial {
u32 base_addr; /* address of registers in physical memory */
u8 port_id; /* uart port number */
u8 enabled; /* 1 if enabled, 0 if disabled */
} config = {
-1U
};
#endif
#if 0
static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
{
/* FIXME: there should be an assertion here if dev_index is >3 */
return (struct s5p_uart *)(EXYNOS5_UART0_BASE + (0x10000 * dev_index));
}
#endif
/*
* The coefficient, used to calculate the baudrate on S5P UARTs is
@ -85,15 +60,13 @@ static const int udivslot[] = {
static void serial_setbrg_dev(void)
{
// struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
struct s5p_uart *uart = (struct s5p_uart *)base_port;
u32 uclk;
u32 baudrate = CONFIG_TTYS0_BAUD;
u32 val;
enum periph_id periph;
periph = exynos5_get_periph_id(base_port);
uclk = clock_get_periph_rate(periph);
// All UARTs share the same clock.
uclk = clock_get_periph_rate(PERIPH_ID_UART3);
val = uclk / baudrate;
writel(val / 16 - 1, &uart->ubrdiv);
@ -117,7 +90,6 @@ static void serial_setbrg_dev(void)
*/
static void exynos5_init_dev(void)
{
// struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
struct s5p_uart *uart = (struct s5p_uart *)base_port;
// TODO initialize with correct peripheral id by base_port.
@ -136,7 +108,6 @@ static void exynos5_init_dev(void)
static int exynos5_uart_err_check(int op)
{
//struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
struct s5p_uart *uart = (struct s5p_uart *)base_port;
unsigned int mask;
@ -162,7 +133,6 @@ static int exynos5_uart_err_check(int op)
*/
static unsigned char exynos5_uart_rx_byte(void)
{
// struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
struct s5p_uart *uart = (struct s5p_uart *)base_port;
/* wait for character to arrive */
@ -180,7 +150,6 @@ static unsigned char exynos5_uart_rx_byte(void)
*/
static void exynos5_uart_tx_byte(unsigned char data)
{
// struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
struct s5p_uart *uart = (struct s5p_uart *)base_port;
/* wait for room in the tx FIFO */
@ -193,6 +162,7 @@ static void exynos5_uart_tx_byte(unsigned char data)
}
#if !defined(__PRE_RAM__)
static const struct console_driver exynos5_uart_console __console = {
.init = exynos5_init_dev,
.tx_byte = exynos5_uart_tx_byte,
@ -205,7 +175,9 @@ uint32_t uartmem_getbaseaddr(void)
{
return base_port;
}
#else
void uart_init(void)
{
exynos5_init_dev();
@ -221,6 +193,8 @@ void uart_tx_byte(unsigned char data)
exynos5_uart_tx_byte(data);
}
void uart_tx_flush(void) {
void uart_tx_flush(void)
{
}
#endif

30
src/cpu/samsung/exynos5250/uart.h
View File

@ -1,13 +1,12 @@
/*
* (C) Copyright 2012 The ChromiumOS Authors
* (C) Copyright 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Heungjun Kim <riverful.kim@samsung.com>
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* Copyright 2012 Google Inc.
* Copyright (C) 2009 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -16,15 +15,11 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This file is based off of arch/arm/include/asm/arch-exynos5/uart.h
* from u-boot.
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __EXYNOS5250_UART_H_
#define __EXYNOS5250_UART_H_
#ifndef CPU_SAMSUNG_EXYNOS5250_UART_H
#define CPU_SAMSUNG_EXYNOS5250_UART_H
#define EXYNOS5_UART0_BASE 0x12c00000
#define EXYNOS5_UART1_BASE 0x12c10000
@ -56,9 +51,4 @@ struct s5p_uart {
unsigned char res3[0xffd0];
};
static inline int s5p_uart_divslot(void)
{
return 0;
}
#endif

6
src/cpu/samsung/exynos5250/wakeup.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc. All rights reserved.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -18,9 +18,7 @@
*/
#include <console/console.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/exynos5-common.h>
#include "power.h"
#include "wakeup.h"
void wakeup(void)

13
src/cpu/samsung/exynos5250/wakeup.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -17,8 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef WAKEUP_H
#define WAKEUP_H
#ifndef CPU_SAMSUNG_EXYNOS5250_WAKEUP_H
#define CPU_SAMSUNG_EXYNOS5250_WAKEUP_H
/* Power Down Modes */
#define S5P_CHECK_SLEEP 0x00000BAD
#define S5P_CHECK_DIDLE 0xBAD00000
#define S5P_CHECK_LPA 0xABAD0000
enum {
// A normal boot (not suspend/resume)
@ -34,4 +39,4 @@ int wakeup_need_reset(void);
int get_wakeup_state(void);
void wakeup(void);
#endif /* WAKEUP_H */
#endif /* CPU_SAMSUNG_EXYNOS5250_WAKEUP_H */

57
src/cpu/samsung/exynos5250/watchdog.h
View File

@ -1,57 +0,0 @@
/*
* Copyright (C) 2011 Samsung Electronics
* Heungjun Kim <riverful.kim@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_COMMON_WATCHDOG_H_
#define __ASM_ARM_ARCH_COMMON_WATCHDOG_H_
#define WTCON_RESET_OFFSET 0
#define WTCON_INTEN_OFFSET 2
#define WTCON_CLKSEL_OFFSET 3
#define WTCON_EN_OFFSET 5
#define WTCON_PRE_OFFSET 8
#define WTCON_CLK_16 0x0
#define WTCON_CLK_32 0x1
#define WTCON_CLK_64 0x2
#define WTCON_CLK_128 0x3
#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
#ifndef __ASSEMBLER__
struct s5p_watchdog {
unsigned int wtcon;
unsigned int wtdat;
unsigned int wtcnt;
unsigned int wtclrint;
};
/* functions */
void wdt_stop(void);
void wdt_start(unsigned int timeout);
#endif /* __ASSEMBLER__ */
#endif

59
src/cpu/samsung/exynos5250/wdt.c
View File

@ -1,59 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/watchdog.h>
#define PRESCALER_VAL 255
void wdt_stop(void)
{
struct s5p_watchdog *wdt =
samsung_get_base_watchdog();
unsigned int wtcon;
wtcon = readl(&wdt->wtcon);
wtcon &= ~(WTCON_EN | WTCON_INT | WTCON_RESET);
writel(wtcon, &wdt->wtcon);
}
void wdt_start(unsigned int timeout)
{
struct s5p_watchdog *wdt =
samsung_get_base_watchdog();
unsigned int wtcon;
wdt_stop();
wtcon = readl(&wdt->wtcon);
wtcon |= (WTCON_EN | WTCON_CLK(WTCON_CLK_128));
wtcon &= ~WTCON_INT;
wtcon |= WTCON_RESET;
wtcon |= WTCON_PRESCALER(PRESCALER_VAL);
writel(timeout, &wdt->wtdat);
writel(timeout, &wdt->wtcnt);
writel(wtcon, &wdt->wtcon);
}

22
src/drivers/maxim/max77686/max77686.c
View File

@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
#include <console/console.h>
#include <arch/io.h>
#include <common.h>
#include <device/i2c.h>
#include "max77686.h"
@ -131,7 +131,7 @@ static int max77686_enablereg(unsigned int bus, enum max77686_regnum reg, int en
ret = max77686_i2c_read(bus, MAX77686_I2C_ADDR, pmic->reg_enaddr,
&read_data);
if (ret != 0) {
debug("max77686 i2c read failed.\n");
printk(BIOS_DEBUG, "max77686 i2c read failed.\n");
return -1;
}
@ -147,7 +147,7 @@ static int max77686_enablereg(unsigned int bus, enum max77686_regnum reg, int en
ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR,
pmic->reg_enaddr, read_data);
if (ret != 0) {
debug("max77686 i2c write failed.\n");
printk(BIOS_DEBUG, "max77686 i2c write failed.\n");
return -1;
}
@ -165,13 +165,13 @@ int max77686_volsetting(unsigned int bus, enum max77686_regnum reg,
pmic = &max77686_param[reg];
if (pmic->vol_addr == 0) {
debug("not a voltage register.\n");
printk(BIOS_DEBUG, "not a voltage register.\n");
return -1;
}
ret = max77686_i2c_read(bus, MAX77686_I2C_ADDR, pmic->vol_addr, &read_data);
if (ret != 0) {
debug("max77686 i2c read failed.\n");
printk(BIOS_DEBUG, "max77686 i2c read failed.\n");
return -1;
}
@ -181,7 +181,7 @@ int max77686_volsetting(unsigned int bus, enum max77686_regnum reg,
vol_level = (volt - (u32)pmic->vol_min) * 1000;
if (vol_level < 0) {
debug("Not a valid voltage level to set\n");
printk(BIOS_DEBUG, "Not a valid voltage level to set\n");
return -1;
}
vol_level /= (u32)pmic->vol_div;
@ -191,13 +191,13 @@ int max77686_volsetting(unsigned int bus, enum max77686_regnum reg,
ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, pmic->vol_addr, read_data);
if (ret != 0) {
debug("max77686 i2c write failed.\n");
printk(BIOS_DEBUG, "max77686 i2c write failed.\n");
return -1;
}
ret = max77686_enablereg(bus, reg, enable);
if (ret != 0) {
debug("Failed to enable buck/ldo.\n");
printk(BIOS_DEBUG, "Failed to enable buck/ldo.\n");
return -1;
}
return 0;
@ -215,7 +215,7 @@ int max77686_disable_backup_batt(unsigned int bus)
ret = max77686_i2c_read(bus, MAX77686_I2C_ADDR, REG_BBAT, &val);
if (ret) {
debug("max77686 i2c read failed\n");
printk(BIOS_DEBUG, "max77686 i2c read failed\n");
return ret;
}
@ -228,7 +228,7 @@ int max77686_disable_backup_batt(unsigned int bus)
val &= ~BBAT_BBCHOSTEN_MASK;
ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, REG_BBAT, val);
if (ret) {
debug("max77686 i2c write failed\n");
printk(BIOS_DEBUG, "max77686 i2c write failed\n");
return -1;
}
@ -236,7 +236,7 @@ int max77686_disable_backup_batt(unsigned int bus)
val |= BBAT_BBCVS_MASK;
ret = max77686_i2c_write(bus, MAX77686_I2C_ADDR, REG_BBAT, val);
if (ret) {
debug("max77686 i2c write failed\n");
printk(BIOS_DEBUG, "max77686 i2c write failed\n");
return -1;
}

63
src/include/gpio.h
View File

@ -1,63 +0,0 @@
/*
* Copyright 2012, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of Google Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef GPIO_H
#define GPIO_H
enum gpio_types {
GPIO_IN,
GPIO_OUT,
GPIO_ALT, /* catch-all for alternate functions */
};
/*
* Many-value logic (3 states). This can be used for inputs whereby presence
* of external pull-up or pull-down resistors can be added to overcome internal
* pull-ups/pull-downs and force a single value.
*
* Thus, external pull resistors can force a 0 or 1 and if the value changes
* along with internal pull-up/down enable then the input is floating.
*
* Vpd | Vpu | MVL
* -----------------
* 0 | 0 | 0
* -----------------
* 0 | 1 | Z <-- floating input will follow internal pull up/down
* -----------------
* 1 | 1 | 1
*/
enum mvl3 {
LOGIC_0,
LOGIC_1,
LOGIC_Z, /* high impedence / tri-stated / floating */
};
#endif /* GPIO_H */

4
src/mainboard/emulation/qemu-armv7/romstage.c
View File

@ -14,18 +14,16 @@
*/
#include <cbfs.h>
#include <common.h>
#include <console/console.h>
#include <arch/stages.h>
void main(void)
{
void *entry;
console_init();
printk(BIOS_INFO, "hello from romstage\n");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
stage_exit(entry);
}

1
src/mainboard/google/snow/Kconfig
View File

@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select EC_GOOGLE_CHROMEEC_I2C
select BOARD_ROMSIZE_KB_4096
select DRIVER_MAXIM_MAX77686
select EXYNOS_DISPLAYPORT
select CHROMEOS
select DRIVER_TI_TPS65090
select MAINBOARD_HAS_NATIVE_VGA_INIT

2
src/mainboard/google/snow/Makefile.inc
View File

@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Google Inc.
## Copyright 2012 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by

2
src/mainboard/google/snow/chromeos.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

2
src/mainboard/google/snow/devicetree.cb
View File

@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Google Inc.
## Copyright 2012 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by

2
src/mainboard/google/snow/exynos5250.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

8
src/mainboard/google/snow/mainboard.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -28,15 +28,13 @@
#include <boot/coreboot_tables.h>
#include <arch/cache.h>
#include <arch/exception.h>
#include <arch/gpio.h>
#include <cpu/samsung/exynos5250/exynos-tmu.h>
#include <cpu/samsung/exynos5250/tmu.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/i2c.h>
#include <cpu/samsung/exynos5250/s5p-dp-core.h>
#include <cpu/samsung/exynos5250/dp-core.h>
#include "exynos5250.h"

5
src/mainboard/google/snow/memory.c
View File

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Samsung Electronics
* Copyright (C) 2013 Google Inc.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -22,11 +22,10 @@
#include <stdlib.h>
#include <console/console.h>
#include <gpio.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/dmc.h>
#include <cpu/samsung/exynos5250/clock_init.h>
#include <cpu/samsung/exynos5250/clk.h>
const struct mem_timings mem_timings[] = {
{

3
src/mainboard/google/snow/romstage.c
View File

@ -21,10 +21,8 @@
#include <armv7.h>
#include <cbfs.h>
#include <common.h>
#include <arch/cache.h>
#include <arch/gpio.h>
#include <cpu/samsung/exynos5250/i2c.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
@ -33,7 +31,6 @@
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/clock_init.h>
#include <cpu/samsung/exynos5250/wakeup.h>
#include <console/console.h>
#include <arch/stages.h>

8
src/mainboard/google/snow/wakeup.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc. All rights reserved.
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -17,13 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/gpio.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/exynos5-common.h>
#include <cpu/samsung/exynos5250/wakeup.h>
int wakeup_need_reset(void)

1
src/mainboard/ti/beaglebone/romstage.c
View File

@ -21,7 +21,6 @@
#include <armv7.h>
#include <cbfs.h>
#include <common.h>
#include <arch/stages.h>
#include <console/console.h>