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mb/ocp/tiogapass: use IPMI driver functionality for "POST complete" 

Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-12-16 19:56:17 +01:00
parent 61469c7a35
commit 08dc4cf439
2 changed files with 4 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/ocp/tiogapass/devicetree.cb
View File

@ -49,6 +49,7 @@ chip soc/intel/xeon_sp/skx
end end
device domain 0 on device domain 0 on
device gpio 0 alias pch_gpio on end
device pci 00.0 on end # Host bridge device pci 00.0 on end # Host bridge
device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
@ -77,8 +78,11 @@ chip soc/intel/xeon_sp/skx
device pci 1f.0 on device pci 1f.0 on
chip drivers/ipmi # BMC KCS chip drivers/ipmi # BMC KCS
device pnp ca2.0 on end device pnp ca2.0 on end
use pch_gpio as gpio_dev
register "bmc_i2c_address" = "0x20" register "bmc_i2c_address" = "0x20"
register "bmc_boot_timeout" = "90" register "bmc_boot_timeout" = "90"
register "post_complete_gpio" = "GPP_B20"
register "post_complete_invert" = "1"
end end
chip drivers/ipmi/ocp # OCP specific IPMI porting chip drivers/ipmi/ocp # OCP specific IPMI porting
device pnp ca2.1 on end device pnp ca2.1 on end

10
src/mainboard/ocp/tiogapass/ramstage.c
View File

@ -3,9 +3,7 @@
#include <bootstate.h> #include <bootstate.h>
#include <drivers/ipmi/ipmi_ops.h> #include <drivers/ipmi/ipmi_ops.h>
#include <drivers/ocp/dmi/ocp_dmi.h> #include <drivers/ocp/dmi/ocp_dmi.h>
#include <gpio.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <soc/lewisburg_pch_gpio_defs.h>
extern struct fru_info_str fru_strings; extern struct fru_info_str fru_strings;
@ -136,12 +134,6 @@ void mainboard_silicon_init_params(FSPS_UPD *params)
{ {
} }
static void pull_post_complete_pin(void *unused)
{
/* Pull Low post complete pin */
gpio_output(GPP_B20, 0);
}
#if CONFIG(GENERATE_SMBIOS_TABLES) #if CONFIG(GENERATE_SMBIOS_TABLES)
static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current)
{ {
@ -189,5 +181,3 @@ struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable, .enable_dev = mainboard_enable,
.final = mainboard_final, .final = mainboard_final,
}; };
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL);