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Fix all the format string warnings. 

Some other random warnings.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2010-03-22 16:33:25 +00:00
parent 53b0ea4bf2
commit 08e0fb8810
162 changed files with 227 additions and 337 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -97,7 +97,7 @@ static void post_cache_as_ram(void)
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
#else
memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
//memset((void*)CONFIG_RAMBASE, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE - 0xa0000));
#endif
print_debug("Done\r\n");

2
src/cpu/amd/model_gx2/cpubug.c
View File

@ -356,7 +356,7 @@ cpubug(void)
rev = msr.lo & 0xff;
if (rev < 0x20) {
printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n");
printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n", __func__);
return;
}
printk(BIOS_DEBUG, "Doing cpubug fixes for rev 0x%x\n", rev);

9
src/cpu/amd/sc520/sc520.c
View File

@ -12,11 +12,12 @@
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
#include <delay.h>
#include "chip.h"
/* hack for now */
void sc520_udelay(int microseconds) {
static void sc520_udelay(int microseconds) {
volatile int x;
for(x = 0; x < 1000; x++)
;
@ -24,7 +25,7 @@ void sc520_udelay(int microseconds) {
/* looks like we define this now */
void
udelay(int microseconds) {
udelay(unsigned microseconds) {
sc520_udelay(microseconds);
}
/*
@ -46,7 +47,7 @@ static void cpu_init(device_t dev)
* there is no real northbridge, keep it here in cpu.
* Ron wins, he's writing the code.
*/
void sc520_enable_resources(struct device *dev) {
static void sc520_enable_resources(struct device *dev) {
unsigned char command;
printk(BIOS_SPEW, "%s\n", __func__);
@ -100,7 +101,7 @@ static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
printk(BIOS_SPEW, "%s sizek 0x%x\n", __func__, sizek);
printk(BIOS_SPEW, "%s sizek 0x%lx\n", __func__, sizek);
if (!sizek) {
return;
}

2
src/mainboard/amd/dbm690t/mptable.c
View File

@ -38,7 +38,7 @@ extern u32 sbdn_sb600;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "ATI ";

2
src/mainboard/amd/dbm690t/romstage.c
View File

@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);

8
src/mainboard/amd/mahogany/mainboard.c
View File

@ -153,10 +153,10 @@ int add_mainboard_resources(struct lb_memory *mem)
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
printk(BIOS_INFO, "uma_memory_start=0x%x, uma_memory_size=0x%x \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
uma_memory_size);
#endif
}

2
src/mainboard/amd/mahogany/mptable.c
View File

@ -39,7 +39,7 @@ extern u32 sbdn_sb700;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";

2
src/mainboard/amd/mahogany/romstage.c
View File

@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);

8
src/mainboard/amd/mahogany_fam10/mainboard.c
View File

@ -153,10 +153,10 @@ int add_mainboard_resources(struct lb_memory *mem)
* in some circumstances we want the memory mentioned as reserved.
*/
#if (CONFIG_GFXUMA == 1)
printk(BIOS_INFO, "uma_memory_start=0x%x, uma_memory_size=0x%x \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
uma_memory_size);
#endif
}

2
src/mainboard/amd/mahogany_fam10/mptable.c
View File

@ -39,7 +39,7 @@ extern u32 sbdn_sb700;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";

4
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -184,9 +184,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);

2
src/mainboard/amd/pistachio/mptable.c
View File

@ -38,7 +38,7 @@ extern u32 sbdn_sb600;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "ATI ";

2
src/mainboard/amd/pistachio/romstage.c
View File

@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);

2
src/mainboard/amd/serengeti_cheetah/mptable.c
View File

@ -12,7 +12,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";

2
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -208,7 +208,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_mb_resource_map();
#if 0

5
src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
View File

@ -64,6 +64,11 @@ config MAX_PHYSICAL_CPUS
default 8
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config LOGICAL_CPUS
bool
default n
depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n

2
src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
View File

@ -70,7 +70,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (u8 *)(addr);

2
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -31,7 +31,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";

4
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -186,9 +186,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);

2
src/mainboard/asus/a8n_e/irq_tables.c
View File

@ -78,7 +78,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000. */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/asus/a8n_e/mptable.c
View File

@ -34,7 +34,7 @@ extern unsigned apicid_ck804;
extern unsigned bus_type[256];
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "ASUS ";

2
src/mainboard/asus/a8v-e_se/mptable.c
View File

@ -23,7 +23,7 @@
#include <../../../southbridge/via/vt8237r/vt8237r.h>
#include <../../../southbridge/via/k8t890/k8t890.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXB ";

2
src/mainboard/asus/p2b-d/mptable.c
View File

@ -24,7 +24,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";

2
src/mainboard/asus/p2b-ds/mptable.c
View File

@ -24,7 +24,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";

2
src/mainboard/broadcom/blast/irq_tables.c
View File

@ -60,7 +60,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/broadcom/blast/mptable.c
View File

@ -21,7 +21,7 @@ extern unsigned sbdn2;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "BROADCOM";

18
src/mainboard/dell/s1850/reset.c
View File

@ -1,5 +1,5 @@
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
@ -25,19 +25,3 @@ void hard_reset(void)
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}
void full_reset(void)
{
device_t dev;
/* Enable power on after power fail... */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
if (dev != PCI_DEV_INVALID) {
unsigned byte;
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
pci_write_config8(dev, 0xa4, byte);
}
outb(0x0e, 0xcf9);
}

2
src/mainboard/digitallogic/msm586seg/mainboard.c
View File

@ -26,7 +26,7 @@ static void irqdump()
printk(BIOS_ERR, "mmcr is %p\n", mmcr);
for(i = 0; irqlist[i] >= 0; i++) {
irq = mmcr + irqlist[i];
printk(BIOS_ERR, "0x%x register @%p is 0x%lx\n", irqlist[i], irq, *irq);
printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
}
}

2
src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
View File

@ -77,7 +77,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/gigabyte/ga_2761gxdk/mptable.c
View File

@ -35,7 +35,7 @@ extern unsigned apicid_sis966;
extern unsigned bus_type[256];
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "GIGABYTE";

2
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -218,7 +218,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
early_usbdebug_direct_init();
#endif
console_init();
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");

2
src/mainboard/gigabyte/m57sli/irq_tables.c
View File

@ -75,7 +75,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/gigabyte/m57sli/mptable.c
View File

@ -36,7 +36,7 @@ extern unsigned bus_type[256];
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "GIGABYTE";

2
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -232,7 +232,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
early_usbdebug_direct_init();
#endif
console_init();
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");

4
src/mainboard/hp/dl145_g3/mptable.c
View File

@ -43,7 +43,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "HP ";
@ -101,7 +101,7 @@ void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], res->base);
printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
}
}

2
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -236,7 +236,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
// setup_early_ipmi_serial();
pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");

2
src/mainboard/ibm/e325/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "IBM ";

2
src/mainboard/ibm/e326/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "IBM ";

2
src/mainboard/intel/eagleheights/mptable.c
View File

@ -58,7 +58,7 @@
#define RCBA_D29IR 0x3144
#define RCBA_D28IR 0x3146
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "Intel ";

16
src/mainboard/intel/eagleheights/reset.c
View File

@ -20,6 +20,7 @@
*/
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
@ -45,18 +46,3 @@ void hard_reset(void)
{
outb(0x06, 0xcf9);
}
void full_reset(void)
{
device_t dev;
/* Enable power on after power fail... */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_LPC), 0);
if (dev != PCI_DEV_INVALID) {
unsigned byte;
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
pci_write_config8(dev, 0xa4, byte);
}
outb(0x0e, 0xcf9);
}

2
src/mainboard/intel/jarrell/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";

1
src/mainboard/intel/jarrell/reset.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)

2
src/mainboard/intel/mtarvon/mptable.c
View File

@ -26,7 +26,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "Intel ";

2
src/mainboard/intel/truxton/mptable.c
View File

@ -24,7 +24,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "Intel ";

2
src/mainboard/intel/xe7501devkit/mptable.c
View File

@ -142,7 +142,7 @@ void xe7501devkit_register_interrupts(struct mp_config_table *mc)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 15, IOAPIC_ICH3, 15);
}
void* smp_write_config_table(void* v)
static void *smp_write_config_table(void* v)
{
static const char sig[4] = MPC_SIGNATURE;
static const char oem[8] = "INTEL ";

2
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -168,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_mb_resource_map();

2
src/mainboard/iwill/dk8s2/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "IWILL ";

2
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -168,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_default_resource_map();

2
src/mainboard/iwill/dk8x/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "IWILL ";

2
src/mainboard/iwill/dk8x/romstage.c
View File

@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_default_resource_map();

2
src/mainboard/kontron/kt690/mptable.c
View File

@ -38,7 +38,7 @@ extern u32 sbdn_sb600;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "KONTRON ";

2
src/mainboard/kontron/kt690/romstage.c
View File

@ -191,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);

2
src/mainboard/msi/ms7135/irq_tables.c
View File

@ -91,7 +91,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *) (addr);

2
src/mainboard/msi/ms7135/mptable.c
View File

@ -38,7 +38,7 @@ extern unsigned bus_type[256];
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "MSI ";

2
src/mainboard/msi/ms7260/irq_tables.c
View File

@ -71,7 +71,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 and 0x100000. */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/msi/ms7260/mptable.c
View File

@ -33,7 +33,7 @@ extern unsigned bus_type[256];
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "MSI ";

7
src/mainboard/msi/ms7260/romstage.c
View File

@ -190,12 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
console_init();
print_debug("*sysinfo range: [");
print_debug_hex32(sysinfo);
print_debug(",");
print_debug_hex32((unsigned long)sysinfo + sizeof(struct sys_info));
print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
print_debug("\r\n");

2
src/mainboard/msi/ms9185/irq_tables.c
View File

@ -82,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/msi/ms9185/mptable.c
View File

@ -40,7 +40,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[3] = "MSI";

2
src/mainboard/msi/ms9185/romstage.c
View File

@ -203,7 +203,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_ms9185_resource_map();
#if 0

2
src/mainboard/msi/ms9282/irq_tables.c
View File

@ -79,7 +79,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/msi/ms9282/mptable.c
View File

@ -34,7 +34,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "MSI ";

4
src/mainboard/msi/ms9652_fam10/get_bus_conf.c
View File

@ -131,10 +131,10 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n");
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n");
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n", apicid_base);
#endif
m->apicid_mcp55 = apicid_base+0;
}

2
src/mainboard/msi/ms9652_fam10/irq_tables.c
View File

@ -76,7 +76,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/msi/ms9652_fam10/mptable.c
View File

@ -31,7 +31,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "MSI ";

4
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -212,9 +212,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08x\n", cpu_init_detectedx);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);

2
src/mainboard/newisys/khepri/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "NEWISYS ";

2
src/mainboard/nvidia/l1_2pvv/irq_tables.c
View File

@ -76,7 +76,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/nvidia/l1_2pvv/mptable.c
View File

@ -31,7 +31,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "NVIDIA ";

2
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -218,7 +218,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
early_usbdebug_direct_init();
#endif
console_init();
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");

2
src/mainboard/olpc/btest/mainboard.c
View File

@ -61,7 +61,7 @@ static void init_dcon(void) {
/* Enable the DCON */
ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
if (ret != 0)
printk(BIOS_DEBUG, "DCON ENABLE FAILED\n", ret);
printk(BIOS_DEBUG, "DCON ENABLE FAILED %d\n", ret);
}
else
printk(BIOS_DEBUG, "DCON NOT FOUND (%x)\n", rev);

2
src/mainboard/olpc/rev_a/mainboard.c
View File

@ -60,7 +60,7 @@ static void init_dcon(void) {
/* Enable the DCON */
ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
if (ret != 0)
printk(BIOS_DEBUG, "DCON ENABLE FAILED\n", ret);
printk(BIOS_DEBUG, "DCON ENABLE FAILED %d\n", ret);
}
else
printk(BIOS_DEBUG, "DCON NOT FOUND (%x)\n", rev);

1
src/mainboard/rca/rm4100/mainboard_smi.c
View File

@ -22,6 +22,7 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
int mainboard_io_trap_handler(int smif)
{

2
src/mainboard/sunw/ultra40/irq_tables.c
View File

@ -71,7 +71,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/sunw/ultra40/mptable.c
View File

@ -34,7 +34,7 @@ extern unsigned sbdnb;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "SUNW ";

2
src/mainboard/supermicro/h8dme/irq_tables.c
View File

@ -75,7 +75,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/supermicro/h8dme/mptable.c
View File

@ -35,7 +35,7 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "SUPERMIC";

6
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -270,11 +270,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: [");
print_debug_hex32(sysinfo);
print_debug(",");
print_debug_hex32((unsigned long)sysinfo + sizeof(struct sys_info));
print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_mb_resource_map();

2
src/mainboard/supermicro/h8dmr/irq_tables.c
View File

@ -75,7 +75,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/supermicro/h8dmr/mptable.c
View File

@ -35,7 +35,7 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "SUPERMIC";

2
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -203,7 +203,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_mb_resource_map();

2
src/mainboard/supermicro/h8dmr_fam10/irq_tables.c
View File

@ -76,7 +76,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/supermicro/h8dmr_fam10/mptable.c
View File

@ -31,7 +31,7 @@
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "SUPERMIC";

4
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -205,9 +205,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);

2
src/mainboard/supermicro/h8qme_fam10/irq_tables.c
View File

@ -76,7 +76,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/mainboard/supermicro/h8qme_fam10/mptable.c
View File

@ -32,7 +32,7 @@
extern void get_bus_conf(void);
extern unsigned sbdn3;
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "SUPERMIC";

4
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -248,9 +248,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);

2
src/mainboard/supermicro/x6dai_g/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";

17
src/mainboard/supermicro/x6dai_g/reset.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
@ -24,19 +25,3 @@ void hard_reset(void)
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}
void full_reset(void)
{
device_t dev;
/* Enable power on after power fail... */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_6300ESB_LPC), 0);
if (dev != PCI_DEV_INVALID) {
unsigned byte;
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
pci_write_config8(dev, 0xa4, byte);
}
outb(0x0e, 0xcf9);
}

2
src/mainboard/supermicro/x6dhe_g/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";

17
src/mainboard/supermicro/x6dhe_g/reset.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
@ -24,19 +25,3 @@ void hard_reset(void)
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}
void full_reset(void)
{
device_t dev;
/* Enable power on after power fail... */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
if (dev != PCI_DEV_INVALID) {
unsigned byte;
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
pci_write_config8(dev, 0xa4, byte);
}
outb(0x0e, 0xcf9);
}

2
src/mainboard/supermicro/x6dhe_g2/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";

17
src/mainboard/supermicro/x6dhe_g2/reset.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
@ -24,19 +25,3 @@ void hard_reset(void)
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}
void full_reset(void)
{
device_t dev;
/* Enable power on after power fail... */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
if (dev != PCI_DEV_INVALID) {
unsigned byte;
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
pci_write_config8(dev, 0xa4, byte);
}
outb(0x0e, 0xcf9);
}

2
src/mainboard/supermicro/x6dhr_ig/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";

17
src/mainboard/supermicro/x6dhr_ig/reset.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
@ -24,19 +25,3 @@ void hard_reset(void)
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}
void full_reset(void)
{
device_t dev;
/* Enable power on after power fail... */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
if (dev != PCI_DEV_INVALID) {
unsigned byte;
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
pci_write_config8(dev, 0xa4, byte);
}
outb(0x0e, 0xcf9);
}

2
src/mainboard/supermicro/x6dhr_ig2/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";

17
src/mainboard/supermicro/x6dhr_ig2/reset.c
View File

@ -1,4 +1,5 @@
#include <arch/io.h>
#include <reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if !defined (__ROMCC__) && !defined (__PRE_RAM__)
@ -24,19 +25,3 @@ void hard_reset(void)
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}
void full_reset(void)
{
device_t dev;
/* Enable power on after power fail... */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_LPC), 0);
if (dev != PCI_DEV_INVALID) {
unsigned byte;
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
pci_write_config8(dev, 0xa4, byte);
}
outb(0x0e, 0xcf9);
}

2
src/mainboard/technexion/tim5690/mptable.c
View File

@ -38,7 +38,7 @@ extern u32 sbdn_sb600;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "ATI ";

2
src/mainboard/technexion/tim5690/romstage.c
View File

@ -198,7 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl now; */
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n",
printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n",
sysinfo->nodes, sysinfo->ctrl, spd_addr);
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);

2
src/mainboard/technexion/tim8690/mptable.c
View File

@ -38,7 +38,7 @@ extern u32 sbdn_sb600;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "ATI ";

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