AMD K8: Remove some excessive preprocessor use
Tests on CPUID are valid regardless of revision. Change-Id: I5a3a01baca2c0ecfb018ca7965994ba74889a2e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8337 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -41,12 +41,15 @@ void cpus_ready_for_init(void)
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}
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#endif
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#if !CONFIG_K8_REV_F_SUPPORT
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int is_e0_later_in_bsp(int nodeid)
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{
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uint32_t val;
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uint32_t val_old;
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int e0_later;
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if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
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return 1;
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if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0
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return !is_cpu_pre_e0();
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}
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@ -67,18 +70,19 @@ int is_e0_later_in_bsp(int nodeid)
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return e0_later;
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}
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#endif
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#if CONFIG_K8_REV_F_SUPPORT
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int is_cpu_f0_in_bsp(int nodeid)
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{
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uint32_t dword;
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device_t dev;
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if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
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return 0;
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dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 3));
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dword = pci_read_config32(dev, 0xfc);
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return (dword & 0xfff00) == 0x40f00;
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}
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#endif
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#define MCI_STATUS 0x401
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@ -278,18 +282,13 @@ static void init_ecc_memory(unsigned node_id)
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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unsigned long hole_startk = 0;
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#if !CONFIG_K8_REV_F_SUPPORT
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if (!is_cpu_pre_e0()) {
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#endif
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if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT) || !is_cpu_pre_e0()) {
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uint32_t val;
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val = pci_read_config32(f1_dev, 0xf0);
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if (val & 1) {
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hole_startk = ((val & (0xff << 24)) >> 10);
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}
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#if !CONFIG_K8_REV_F_SUPPORT
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}
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#endif
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#endif
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/* Don't start too early */
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@ -347,10 +346,10 @@ static void init_ecc_memory(unsigned node_id)
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printk(BIOS_DEBUG, " done\n");
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}
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static inline void k8_errata(void)
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static void k8_pre_f_errata(void)
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{
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msr_t msr;
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#if !CONFIG_K8_REV_F_SUPPORT
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if (is_cpu_pre_c0()) {
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/* Erratum 63... */
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msr = rdmsr(HWCR_MSR);
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@ -414,18 +413,17 @@ static inline void k8_errata(void)
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msr.hi |= 1;
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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#endif
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}
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static void k8_errata(void)
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{
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msr_t msr;
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#if !CONFIG_K8_REV_F_SUPPORT
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/* I can't touch this msr on early buggy cpus */
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if (!is_cpu_pre_b3())
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#endif
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{
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if (!is_cpu_pre_b3()) {
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msr = rdmsr(NB_CFG_MSR);
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#if !CONFIG_K8_REV_F_SUPPORT
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if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
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if (is_cpu_pre_d0() && !is_cpu_pre_c0()) {
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/* D0 later don't need it */
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/* Erratum 86 Disable data masking on C0 and
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* later processor revs.
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@ -433,7 +431,7 @@ static inline void k8_errata(void)
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*/
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msr.hi |= 1 << (36 - 32);
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}
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#endif
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/* Erratum 89 ... */
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/* Erratum 89 is mistakenly labeled as 88 in AMD pub #25759
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* It is correctly labeled as 89 on page 49 of the document
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@ -448,12 +446,11 @@ static inline void k8_errata(void)
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wrmsr(NB_CFG_MSR, msr);
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}
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/* Erratum 122 */
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msr = rdmsr(HWCR_MSR);
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msr.lo |= 1 << 6;
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wrmsr(HWCR_MSR, msr);
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}
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static void model_fxx_init(device_t dev)
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@ -479,6 +476,9 @@ static void model_fxx_init(device_t dev)
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wrmsr(MCI_STATUS + (i * 4), msr);
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}
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if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
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k8_pre_f_errata();
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k8_errata();
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enable_cache();
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@ -2,7 +2,6 @@
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int init_processor_name(void);
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#if !CONFIG_K8_REV_F_SUPPORT
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static inline int is_cpu_rev_a0(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f00;
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@ -48,13 +47,32 @@ static inline int is_cpu_e0(void)
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return (cpuid_eax(1) & 0xfff00) == 0x20f00;
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}
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//AMD_F0_SUPPORT
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static inline int is_cpu_pre_f0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x40f00;
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}
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static inline int is_cpu_f0(void)
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{
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return (cpuid_eax(1) & 0xfff00) == 0x40f00;
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}
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static inline int is_cpu_pre_f2(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
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}
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#ifdef __PRE_RAM__
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static int is_e0_later_in_bsp(int nodeid)
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static inline int is_e0_later_in_bsp(int nodeid)
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{
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uint32_t val;
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uint32_t val_old;
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int e0_later;
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if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
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return 1;
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if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
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return !is_cpu_pre_e0();
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}
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@ -73,50 +91,32 @@ static int is_e0_later_in_bsp(int nodeid)
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return e0_later;
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}
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#else
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int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c
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#endif
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#endif
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#if CONFIG_K8_REV_F_SUPPORT
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//AMD_F0_SUPPORT
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static inline int is_cpu_pre_f0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x40f00;
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}
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static inline int is_cpu_f0(void)
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{
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return (cpuid_eax(1) & 0xfff00) == 0x40f00;
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}
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static inline int is_cpu_pre_f2(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
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}
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#ifdef __PRE_RAM__
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//AMD_F0_SUPPORT
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static inline int is_cpu_f0_in_bsp(int nodeid)
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{
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uint32_t dword;
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device_t dev;
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if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
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return 0;
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dev = PCI_DEV(0, 0x18+nodeid, 3);
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dword = pci_read_config32(dev, 0xfc);
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return (dword & 0xfff00) == 0x40f00;
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}
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static inline int is_cpu_pre_f2_in_bsp(int nodeid)
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{
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uint32_t dword;
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device_t dev;
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if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT))
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return 1;
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dev = PCI_DEV(0, 0x18+nodeid, 3);
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dword = pci_read_config32(dev, 0xfc);
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return (dword & 0xfff0f) < 0x40f02;
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}
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#else
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int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c
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#endif
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int is_e0_later_in_bsp(int nodeid);
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int is_cpu_f0_in_bsp(int nodeid);
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#endif
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