GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Intel 82810 and 82830: always room for PCI memory 

No need for the test, tomk is at most 1GB on these chipsets.
Even if there was no room, adjusting the memory resource would not
not divert accesses in the hardware from DRAM to PCI.

Change-Id: I2213b8d9d2e6ab8da8fd3e8081cc62bb05b6b316
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1369
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
Kyösti Mälkki 2012-07-27 08:40:46 +03:00 committed by Anton Kochkov
parent b5f5652e0f
commit 08ef498d0b
2 changed files with 4 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/northbridge/intel/i82810/northbridge.c
View File

@ -87,15 +87,13 @@ static int translate_i82810_to_mb[] = {
static void pci_domain_set_resources(device_t dev) static void pci_domain_set_resources(device_t dev)
{ {
device_t mc_dev; device_t mc_dev;
uint32_t pci_tolm;
int igd_memory = 0; int igd_memory = 0;
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children; mc_dev = dev->link_list->children;
if (!mc_dev) if (!mc_dev)
return; return;
unsigned long tomk, tolmk; unsigned long tomk;
int idx, drp_value; int idx, drp_value;
u8 reg8; u8 reg8;
@ -132,17 +130,10 @@ static void pci_domain_set_resources(device_t dev)
uma_memory_size = igd_memory * 1024ULL; uma_memory_size = igd_memory * 1024ULL;
printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
/* Compute the top of low memory. */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory. */
tolmk = tomk;
}
/* Report the memory regions. */ /* Report the memory regions. */
idx = 10; idx = 10;
ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768); ram_resource(dev, idx++, 768, tomk - 768);
#if CONFIG_WRITE_HIGH_TABLES #if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */ /* Leave some space for ACPI, PIRQ and MP tables */

13
src/northbridge/intel/i82830/northbridge.c
View File

@ -67,15 +67,13 @@ int add_northbridge_resources(struct lb_memory *mem)
static void pci_domain_set_resources(device_t dev) static void pci_domain_set_resources(device_t dev)
{ {
device_t mc_dev; device_t mc_dev;
uint32_t pci_tolm;
int igd_memory = 0; int igd_memory = 0;
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children; mc_dev = dev->link_list->children;
if (!mc_dev) if (!mc_dev)
return; return;
unsigned long tomk, tolmk; unsigned long tomk;
int idx; int idx;
if (CONFIG_VIDEO_MB == 512) { if (CONFIG_VIDEO_MB == 512) {
@ -98,18 +96,11 @@ static void pci_domain_set_resources(device_t dev)
uma_memory_size = igd_memory * 1024ULL; uma_memory_size = igd_memory * 1024ULL;
printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
/* Compute the top of low memory. */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory. */
tolmk = tomk;
}
/* Report the memory regions. */ /* Report the memory regions. */
idx = 10; idx = 10;
ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, 256); ram_resource(dev, idx++, 768, 256);
ram_resource(dev, idx++, 1024, tolmk - 1024); ram_resource(dev, idx++, 1024, tomk - 1024);
assign_resources(dev->link_list); assign_resources(dev->link_list);