src/mainboard: Fix typo

Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/advansus/a785e-i/resourcemap.c

@@ -119,7 +119,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/amd/bimini_fam10/mainboard.c

@@ -29,7 +29,7 @@ static void enable_int_gfx(void)
 
 	volatile u8 *gpio_reg;
 
-	pm_iowrite(0xEA, 0x01);	/* diable the PCIB */
+	pm_iowrite(0xEA, 0x01);	/* disable the PCIB */
 	/* Disable Gec */
 	byte = pm_ioread(0xF6);
 	byte |= 1;

src/mainboard/amd/bimini_fam10/resourcemap.c

@@ -120,7 +120,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/amd/db-ft3b-lc/mptable.c

@@ -30,7 +30,7 @@ static void *smp_write_config_table(void *v)
 	struct mp_config_table *mc;
 	int bus_isa;
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/amd/lamar/mptable.c

@@ -44,7 +44,7 @@ static void *smp_write_config_table(void *v)
 	struct mp_config_table *mc;
 	int bus_isa;
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/amd/mahogany_fam10/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/amd/persimmon/mainboard.c

@@ -85,7 +85,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  */
 /*
  * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  * off-chip devices should get mapped to PIRQH/E/F/G.

src/mainboard/amd/persimmon/mptable.c

@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c

@@ -119,7 +119,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/amd/south_station/mainboard.c

@@ -18,7 +18,7 @@
 #include <device/device.h>
 
 #include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
+#include "SBPLATFORM.h" 	/* Platform Specific Definitions */
 
 /**
  * Southstation using SB GPIO 17/18 to control the Red/Green LED

src/mainboard/amd/tilapia_fam10/resourcemap.c

@@ -119,7 +119,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/amd/torpedo/gpio.h

@@ -298,8 +298,8 @@
 #define GPIO_187_SELECT     FUNCTION2           // USED AS AC LED INDICATOR, LOW ACTIVE
 #define GPIO_188_SELECT     FUNCTION2           // default used AS BATT LED INDICATOR, LOW ACTIVE
                                                 // option for HDMI CEC signal OW ACTIVE
-#define GPIO_189_SELECT     FUNCTION1           // USED AS AC_OK RECIEVER, INPUT, low active
+#define GPIO_189_SELECT     FUNCTION1           // USED AS AC_OK RECEIVER, INPUT, low active
-#define GPIO_190_SELECT     FUNCTION1           // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
+#define GPIO_190_SELECT     FUNCTION1           // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT
 #define GPIO_191_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, DATA
 #define GPIO_192_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, CLK
 #define GPIO_193_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,

src/mainboard/amd/torpedo/platform_cfg.h

@@ -329,7 +329,7 @@
 /**
  *   @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER
  *    @li <b>0</b> - Auto   : Detect Azalia controller automatically.
- *    @li <b>1</b> - Diable : Disable Azalia controller.
+ *    @li <b>1</b> - Disable : Disable Azalia controller.
  *    @li <b>2</b> - Enable : Enable Azalia controller.
  */
 #define INCHIP_AZALIA_CONTROLLER   2

src/mainboard/amd/union_station/mainboard.c

@@ -17,7 +17,7 @@
 #include <device/device.h>
 
 #include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
+#include "SBPLATFORM.h" 	/* Platform Specific Definitions */
 
 /**********************************************
  * Enable the dedicated functions of the board.

src/mainboard/asus/am1i-a/mptable.c

@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/asus/kcma-d8/resourcemap.c

@@ -124,7 +124,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
@@ -379,7 +379,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/asus/kfsn4-dre/resourcemap.c

@@ -124,7 +124,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/asus/kgpe-d16/resourcemap.c

@@ -124,7 +124,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
@@ -379,7 +379,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/asus/m4a78-em/mainboard.c

@@ -76,7 +76,7 @@ void set_pcie_reset(void)
 /*
  * justify the dev3 is exist or not
  * NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown if it will work at all for this board.
+ * It is completely unknown if it will work at all for this board.
  */
 int is_dev3_present(void)
 {

src/mainboard/asus/m4a78-em/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/asus/m4a785-m/mainboard.c

@@ -86,7 +86,7 @@ void set_pcie_reset(void)
 /*
  * justify the dev3 is exist or not
  * NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown it it will work at all for ASUS M4A785-M.
+ * It is completely unknown it it will work at all for ASUS M4A785-M.
  */
 int is_dev3_present(void)
 {

src/mainboard/asus/m4a785-m/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/asus/m5a88-v/resourcemap.c

@@ -119,7 +119,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/avalue/eax-785e/resourcemap.c

@@ -119,7 +119,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/bap/ode_e20XX/mptable.c

@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/biostar/am1ml/mptable.c

@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/elmex/pcm205400/mainboard.c

@@ -84,7 +84,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  */
 /*
  * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  * off-chip devices should get mapped to PIRQH/E/F/G.

src/mainboard/elmex/pcm205400/mptable.c

@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/emulation/qemu-armv7/mainboard.c

@@ -36,7 +36,7 @@ static void init_gfx(void)
 	write32(pl111 + 1, height - 1);
 	/* registers 2, 3 and 5 are ignored by qemu. Set them correctly if
 	   we ever go for real hw.  */
-	/* framebuffer adress offset. Has to be in vram.  */
+	/* framebuffer address offset. Has to be in vram.  */
 	write32(pl111 + 4, framebuffer);
 	write32(pl111 + 7, 0);
 	write32(pl111 + 10, 0xff);

src/mainboard/gigabyte/ma785gm/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/gigabyte/ma785gmt/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/gigabyte/ma78gm/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/gizmosphere/gizmo2/mptable.c

@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/google/daisy/romstage.c

@@ -88,7 +88,7 @@ static void setup_power(int is_resume)
 
 	if (error) {
 		printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error);
-		die("Failed to intialize PMIC.\n");
+		die("Failed to initialize PMIC.\n");
 	}
 }
 

src/mainboard/google/peach_pit/romstage.c

@@ -241,7 +241,7 @@ void main(void)
 	exception_init();
 
 	if (power_init_failed)
-		die("Failed to intialize power.\n");
+		die("Failed to initialize power.\n");
 
 	/* re-initialize PMIC I2C channel after (re-)setting system clocks */
 	i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */

src/mainboard/google/urara/urara_boardid.h

@@ -17,7 +17,7 @@
 #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__
 
 /*
- * List of URARA derivatives board ID defintions. They are stored in uint8_t
+ * List of URARA derivatives board ID definitions. They are stored in uint8_t
  * across the code, using #defines here not to imply any specific size.
  */
 #define URARA_BOARD_ID_BUB	0

src/mainboard/iei/kino-780am2-fam10/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/intel/glkrvp/variants/baseboard/gpio.c

@@ -54,7 +54,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */
 	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */
 	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Ouput/ISH_GPIO_3*/
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Output/ISH_GPIO_3*/
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_32, DN_20K, DEEP, NF1), /* ISH_GPIO_6 */

src/mainboard/jetway/nf81-t56n-lf/mainboard.c

@@ -87,7 +87,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  */
 /*
  * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  * off-chip devices should get mapped to PIRQH/E/F/G.

src/mainboard/jetway/nf81-t56n-lf/mptable.c

@@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/jetway/pa78vm5/resourcemap.c

@@ -122,7 +122,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/msi/ms9652_fam10/resourcemap.c

@@ -122,7 +122,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/pcengines/apu1/mainboard.c

@@ -91,7 +91,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  */
 /*
  * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because of PCI INT_PIN swizzle isnt implemented to match
+ * but because of PCI INT_PIN swizzle isn't implemented to match
  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  * off-chip devices should get mapped to PIRQH/E/F/G.

src/mainboard/pcengines/apu1/mptable.c

@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/pcengines/apu2/mptable.c

@@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v)
 	struct mp_config_table *mc;
 	int bus_isa;
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);

src/mainboard/siemens/mc_tcu3/ptn3460.c

@@ -38,7 +38,7 @@ int ptn3460_init(char *hwi_block)
 		return 1;
 	}
 
-	status = i2c_init(PTN_I2C_CONTROLER);
+	status = i2c_init(PTN_I2C_CONTROLLER);
 	if (status)
 		return (PTN_BUS_ERROR | status);
 
@@ -66,7 +66,7 @@ int ptn3460_init(char *hwi_block)
 	/* Select this table to be emulated */
 	ptn_select_edid(6);
 	/* Read PTN configuration data */
-	status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
+	status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
 			  (u8*)&cfg, PTN_CONFIG_LEN);
 	if (status)
 		return (PTN_BUS_ERROR | status);
@@ -94,7 +94,7 @@ int ptn3460_init(char *hwi_block)
 	cfg.backlight_ctrl = 0;		  /* Enable backlight control */
 
 	/* Write back configuration data to PTN3460 */
-	status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
+	status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
 			   (u8*)&cfg, PTN_CONFIG_LEN);
 	if (status)
 		return (PTN_BUS_ERROR | status);
@@ -114,13 +114,13 @@ int ptn3460_read_edid(u8 edid_num, u8 *data)
 	if (edid_num > PTN_MAX_EDID_NUM)
 		return PTN_INVALID_EDID;
 	/* First enable access to the desired EDID table */
-	status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
+	status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
 			   &edid_num, 1);
 	if (status)
 		return (PTN_BUS_ERROR | status);
 
 	/* Now we can simply read back EDID-data */
-	status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
+	status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
 			  data, PTN_EDID_LEN);
 	if (status)
 		return (PTN_BUS_ERROR | status);
@@ -140,13 +140,13 @@ int ptn3460_write_edid(u8 edid_num, u8 *data)
 	if (edid_num > PTN_MAX_EDID_NUM)
 		return PTN_INVALID_EDID;
 	/* First enable access to the desired EDID table */
-	status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
+	status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
 			   &edid_num, 1);
 	if (status)
 		return (PTN_BUS_ERROR | status);
 
 	/* Now we can simply write EDID-data to ptn3460 */
-	status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
+	status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
 			   data, PTN_EDID_LEN);
 	if (status)
 		return (PTN_BUS_ERROR | status);
@@ -168,7 +168,7 @@ int ptn_select_edid (u8 edid_num)
 		return PTN_INVALID_EDID;
 	/* Enable emulation of the desired EDID table */
 	val = (edid_num << 1) | 1;
-	status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4,
+	status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4,
 			   &val, 1);
 	if (status)
 		return (PTN_BUS_ERROR | status);
@@ -191,7 +191,7 @@ int ptn3460_flash_config(void)
 	flash.cmd = 0x01;	/* perform erase and flash cycle */
 	flash.magic = 0x7845;	/* Magic number to protect flash operation */
 	flash.trigger = 0x56;	/* This value starts flash operation */
-	status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF,
+	status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF,
 			   (u8*)&flash, PTN_FLASH_CFG_LEN);
 	if (status) {
 		return (PTN_BUS_ERROR | status);

src/mainboard/siemens/mc_tcu3/ptn3460.h

@@ -21,7 +21,7 @@
 #include "lcd_panel.h"
 
 #define PTN_SLAVE_ADR		0x20
-#define PTN_I2C_CONTROLER	0
+#define PTN_I2C_CONTROLLER	0
 
 #define PTN_EDID_OFF		0x00
 #define PTN_EDID_LEN		0x80

src/mainboard/supermicro/h8dmr_fam10/resourcemap.c

@@ -122,7 +122,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/supermicro/h8qme_fam10/resourcemap.c

@@ -122,7 +122,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/supermicro/h8scm_fam10/resourcemap.c

@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,

src/mainboard/tyan/s2912_fam10/resourcemap.c

@@ -122,7 +122,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,