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soc/intel/skylake: Enable SATA depending on devicetree configuration 

Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.

Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-07-29 19:57:25 +02:00 committed by Michael Niewöhner
parent 3c0486913f
commit 0901d03085
24 changed files with 14 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/51nb/x210/devicetree.cb
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@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "0"

1
src/mainboard/asrock/h110m/devicetree.cb
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@ -154,7 +154,6 @@ chip soc/intel/skylake
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
# SATA
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
# SATA4 and SATA5 are located in the lower right corner of the board,
# but they are not populated. This is because the same PCB is used to

23
src/mainboard/facebook/monolith/devicetree.cb
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@ -49,18 +49,17 @@ chip soc/intel/skylake
register "HeciEnabled" = "0"
register "EnableLan" = "1"
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 0, \
[2] = 0, \
[3] = 0, \
[4] = 0, \
[5] = 0, \
[6] = 0, \
[7] = 0, \
}"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 0, \
[2] = 0, \
[3] = 0, \
[4] = 0, \
[5] = 0, \
[6] = 0, \
[7] = 0, \
}"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s

1
src/mainboard/google/eve/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -66,7 +66,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/google/glados/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -43,7 +43,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
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@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "1"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
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@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -43,7 +43,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View File

@ -84,7 +84,6 @@ chip soc/intel/skylake
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \

1
src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/skylake
# SATA port 0
register "EnableSata" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"

1
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@ -127,7 +127,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \

1
src/mainboard/intel/saddlebrook/devicetree.cb
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@ -175,7 +175,6 @@ chip soc/intel/skylake
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \

1
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -35,7 +35,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "0"

1
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -46,7 +46,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -28,7 +28,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View File

@ -17,7 +17,6 @@ chip soc/intel/skylake
# SATA configuration
register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \

5
src/soc/intel/skylake/chip.c
View File

@ -166,8 +166,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
}
params->SataEnable = config->EnableSata;
if (config->EnableSata) {
dev = pcidev_path_on_root(PCH_DEVFN_SATA);
params->SataEnable = dev ? dev->enabled : 0;
if (params->SataEnable) {
memcpy(params->SataPortsEnable, config->SataPortsEnable,
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,

1
src/soc/intel/skylake/chip.h
View File

@ -143,7 +143,6 @@ struct soc_intel_skylake_config {
u8 LanClkReqNumber;
/* SATA related */
u8 EnableSata;
enum {
/* Documentation and header files of Skylake FSP disagree on
the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses