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soc/intel/apollolake: Disable HECI2 device reset on S3 resume 

Converged Security Engine (CSE) has a secure variable storage feature.
However, this storage is expected to be reset during S3 resume flow.
Since coreboot does not use secure storage feature, disable HECI2 reset
request. This saves appr. 130ms of resume time.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note
FspMemoryInit time is not significantly different from normal boot
time case.

Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Andrey Petrov 2016-10-03 16:05:20 -07:00 committed by Martin Roth
parent 7692807f4f
commit 0910f4e76f
1 changed files with 9 additions and 0 deletions
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9
src/soc/intel/apollolake/romstage.c
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@ -184,6 +184,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
*/
mupd->FspmConfig.SkipCseRbp =
IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED);
/*
* Converged Security Engine (CSE) has secure storage functionality.
* HECI2 device can be used to access that functionality. However, part
* of S3 resume flow involves resetting HECI2 which takes 136ms. Since
* coreboot does not use secure storage functionality, instruct FSP to
* skip HECI2 reset.
*/
mupd->FspmConfig.EnableS3Heci2 = 0;
}
__attribute__ ((weak))