GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs 

Add Silicon upd settings for LPSS (GSPI/UART/I2C).

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Tan, Lean Sheng 2021-05-26 06:40:56 -07:00 committed by Patrick Georgi
parent cdb81500f1
commit 09133c78dd
3 changed files with 139 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
View File

@ -43,13 +43,71 @@ chip soc/intel/elkhartlake
register "PcieClkSrcClkReq[4]" = "0x4"
register "PcieClkSrcClkReq[5]" = "0x5"
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexI2C6] = PchSerialIoPci,
[PchSerialIoIndexI2C7] = PchSerialIoPci,
}"
register "SerialIoI2cPadsTermination" = "{
[PchSerialIoIndexI2C0] = 1,
[PchSerialIoIndexI2C1] = 1,
[PchSerialIoIndexI2C2] = 1,
[PchSerialIoIndexI2C3] = 1,
[PchSerialIoIndexI2C4] = 1,
[PchSerialIoIndexI2C5] = 1,
[PchSerialIoIndexI2C6] = 1,
[PchSerialIoIndexI2C7] = 1,
}"
register "SerialIoGSpiMode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoHidden,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
}"
register "SerialIoGSpiCsEnable" = "{
[PchSerialIoIndexGSPI0] = 1,
[PchSerialIoIndexGSPI1] = 1,
[PchSerialIoIndexGSPI2] = 1,
}"
register "SerialIoGSpiCsMode" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI2] = 0,
}"
register "SerialIoGSpiCsState" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI2] = 0,
}"
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
register "SerialIoUartDmaEnable" = "{
[PchSerialIoIndexUART0] = 1,
[PchSerialIoIndexUART1] = 1,
[PchSerialIoIndexUART2] = 1,
}"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 08.0 off end # GNA
device pci 09.0 off end # CPU Intel Trace Hub

17
src/soc/intel/elkhartlake/chip.h
View File

@ -166,6 +166,14 @@ struct soc_intel_elkhartlake_config {
uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
* UARTn Default DMA/PIO Mode Enable(1)/Disable(0):
*/
uint8_t SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
* GSPIn Default Chip Enable(1)/Disable(0):
*/
uint8_t SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* GSPIn Default Chip Select Mode:
* 0:Hardware Mode,
@ -178,6 +186,15 @@ struct soc_intel_elkhartlake_config {
* 1: High
*/
uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* SerialIo I2C Pads Termination Config:
* 0x0:Hardware default,
* 0x1:None,
* 0x13:1kOhm weak pull-up,
* 0x15:5kOhm weak pull-up,
* 0x19:20kOhm weak pull-up
*/
uint8_t SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX];
/*
* TraceHubMode config

62
src/soc/intel/elkhartlake/fsp_params.c
View File

@ -13,6 +13,7 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
#include <string.h>
/*
* ME End of Post configuration
@ -45,7 +46,66 @@ static const pci_devfn_t serial_io_dev[] = {
static void parse_devicetree(FSP_S_CONFIG *params)
{
/* TODO: Update with UPD override as FSP matures */
const struct soc_intel_elkhartlake_config *config = config_of_soc();
/* LPSS controllers configuration */
/* I2C */
_Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >=
ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode,
sizeof(config->SerialIoI2cMode));
_Static_assert(ARRAY_SIZE(params->PchSerialIoI2cPadsTermination) >=
ARRAY_SIZE(config->SerialIoI2cPadsTermination),
"copy buffer overflow!");
memcpy(params->PchSerialIoI2cPadsTermination, config->SerialIoI2cPadsTermination,
sizeof(config->SerialIoI2cPadsTermination));
params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09; //GPIO native mode for GPP_H9
params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08; //GPIO native mode for GPP_H8
/* GSPI */
_Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >=
ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!");
memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode,
sizeof(config->SerialIoGSpiMode));
_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsEnable) >=
ARRAY_SIZE(config->SerialIoGSpiCsEnable), "copy buffer overflow!");
memcpy(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable,
sizeof(config->SerialIoGSpiCsEnable));
_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >=
ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!");
memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode,
sizeof(config->SerialIoGSpiCsMode));
_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >=
ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!");
memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState,
sizeof(config->SerialIoGSpiCsState));
params->SerialIoSpiCsPolarity[2] = 0;
/* UART */
_Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >=
ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!");
memcpy(params->SerialIoUartMode, config->SerialIoUartMode,
sizeof(config->SerialIoUartMode));
_Static_assert(ARRAY_SIZE(params->SerialIoUartDmaEnable) >=
ARRAY_SIZE(config->SerialIoUartDmaEnable), "copy buffer overflow!");
memcpy(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable,
sizeof(config->SerialIoUartDmaEnable));
params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; //GPIO native mode for GPP_T15
params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; //GPIO native mode for GPP_T14
params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; //GPIO native mode for GPP_T12
params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; //GPIO native mode for GPP_T13
/* Provide correct UART number for FSP debug logs */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
}
/* UPD parameters to be initialized before SiliconInit */