intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER

Note that due to UNKNOWN_TSC_RATE, each stage will have
a slow run of calibrate_tsc_with_pit(). This is easy enough
to fix with followup implementation of tsc_freq_mhz() for
the cpu.

Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/slot_1/Kconfig

@@ -24,7 +24,8 @@ config SLOT_SPECIFIC_OPTIONS # dummy
 	select CPU_INTEL_MODEL_6BX
 	select CPU_INTEL_MODEL_6XX
 	select NO_SMM
-	select NO_MONOTONIC_TIMER
+	select UDELAY_TSC
+	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
 
 config DCACHE_RAM_BASE

src/northbridge/intel/i440bx/Kconfig

@@ -17,7 +17,6 @@ config NORTHBRIDGE_INTEL_I440BX
 	bool
 	select NO_MMCONF_SUPPORT
 	select HAVE_DEBUG_RAM_SETUP
-	select UDELAY_IO
 
 config SDRAMPWR_4DIMM
 	bool