mb/google/brya/var/redrix: Select camera module based on SSFC value
This patch has changes to support multiple camera modules, base on the value set in the SSFC_CONFIG. BUG=b:198235323 TEST=tested the changes with redrix 5MP(ov5675/hi556) camera. Change-Id: I71c8355617171ec7d08862759b87d4bf12ce2924 Signed-off-by: Arec Kao <arec.kao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57272 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -32,6 +32,7 @@ config BOARD_GOOGLE_REDRIX
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select CHROMEOS_DSM_CALIB if CHROMEOS
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select CHROMEOS_DSM_CALIB if CHROMEOS
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select DRIVERS_I2C_MAX98390
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select DRIVERS_I2C_MAX98390
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_INTEL_MIPI_CAMERA
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select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_COMMON_BLOCK_IPU
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select DRIVERS_GENESYSLOGIC_GL9755
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select DRIVERS_GENESYSLOGIC_GL9755
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select DRIVERS_GFX_GENERIC
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select DRIVERS_GFX_GENERIC
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@ -20,6 +20,11 @@ fw_config
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option PRIVACY_SCREEN_ABSENT 0
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option PRIVACY_SCREEN_ABSENT 0
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option PRIVACY_SCREEN 1
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option PRIVACY_SCREEN 1
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end
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end
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field CAMERA_UFC 38 39
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option CAMERA_NONE 0
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option CAMERA_OV5675 1
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option CAMERA_HI556 2
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end
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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@ -271,7 +276,7 @@ chip soc/intel/alderlake
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register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
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register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
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register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
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register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
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register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #PP3300_FCAM_X
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register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #EN_UCAM_LED_PWR
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register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR
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register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR
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register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
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register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
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@ -289,7 +294,50 @@ chip soc/intel/alderlake
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register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
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register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
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register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
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register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
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register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
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register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
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device i2c 36 on end
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device i2c 36 on
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probe CAMERA_UFC CAMERA_NONE
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probe CAMERA_UFC CAMERA_OV5675
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end
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end
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chip drivers/intel/mipi_camera
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register "acpi_hid" = ""INT3537""
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register "acpi_uid" = "0"
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register "acpi_name" = ""CAM0""
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register "chip_name" = ""Hi-556 Camera""
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register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
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register "ssdb.lanes_used" = "2"
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register "ssdb.link_used" = "1"
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register "num_freq_entries" = "1"
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register "link_freq[0]" = "437000000"
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register "remote_name" = ""IPU0""
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register "has_power_resource" = "1"
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#Controls
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register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
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register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
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register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #EN_UCAM_LED_PWR
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register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR
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register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset
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#_ON
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register "on_seq.ops_cnt" = "5"
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register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
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register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
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register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
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register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
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register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
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#_OFF
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register "off_seq.ops_cnt" = "4"
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register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
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register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
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register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
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register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
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device i2c 20 on
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probe CAMERA_UFC CAMERA_HI556
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end
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end
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end
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chip drivers/intel/mipi_camera
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chip drivers/intel/mipi_camera
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register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
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register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
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@ -305,7 +353,6 @@ chip soc/intel/alderlake
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register "nvm_readonly" = "1"
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register "nvm_readonly" = "1"
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register "nvm_width" = "0x10"
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register "nvm_width" = "0x10"
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register "nvm_compat" = ""atmel,24c64""
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register "nvm_compat" = ""atmel,24c64""
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device i2c 50 on end
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device i2c 50 on end
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end
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end
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