src/acpi to src/lib: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/acpi/acpi.c

@@ -1937,15 +1937,15 @@ int get_acpi_table_revision(enum acpi_tables table)
 		return 2;
 	case TPM2:
 		return 4;
-	case SSDT: /* ACPI 3.0 upto 6.3: 2 */
+	case SSDT: /* ACPI 3.0 up to 6.3: 2 */
 		return 2;
-	case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */
+	case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.3: 3 */
 		return 1; /* TODO Should probably be upgraded to 2 */
 	case HMAT: /* ACPI 6.4: 2 */
 		return 2;
 	case DMAR:
 		return 1;
-	case SLIT: /* ACPI 2.0 upto 6.3: 1 */
+	case SLIT: /* ACPI 2.0 up to 6.3: 1 */
 		return 1;
 	case SPMI: /* IMPI 2.0 */
 		return 5;
@@ -1957,13 +1957,13 @@ int get_acpi_table_revision(enum acpi_tables table)
 		return IVRS_FORMAT_MIXED;
 	case DBG2:
 		return 0;
-	case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */
+	case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 up to 6.3: 2 */
 		return 1;
-	case RSDT: /* ACPI 1.0 upto 6.3: 1 */
+	case RSDT: /* ACPI 1.0 up to 6.3: 1 */
 		return 1;
-	case XSDT: /* ACPI 2.0 upto 6.3: 1 */
+	case XSDT: /* ACPI 2.0 up to 6.3: 1 */
 		return 1;
-	case RSDP: /* ACPI 2.0 upto 6.3: 2 */
+	case RSDP: /* ACPI 2.0 up to 6.3: 2 */
 		return 2;
 	case EINJ:
 		return 1;

src/acpi/device.c

@@ -139,7 +139,7 @@ static ssize_t acpi_device_path_fill(const struct device *dev, char *buf,
 
 /*
  * Warning: just as with dev_path() this uses a static buffer
- * so should not be called mulitple times in one statement
+ * so should not be called multiple times in one statement
  */
 const char *acpi_device_path(const struct device *dev)
 {

src/arch/arm/armv7/cpu.S

@@ -16,7 +16,7 @@
  * the LSB of the set field, but the latter contains the LSB of the way field
  * minus the highest valid set field... such that when you subtract it from a
  * [way:0:level] field you end up with a [way - 1:highest_set:level] field
- * through the magic of double subtraction. It's quite ingenius, really.
+ * through the magic of double subtraction. It's quite ingenious, really.
  * Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without
  * needing to write to memory.
  *

src/arch/arm64/include/arch/asm.h

@@ -19,7 +19,7 @@
 	.size name, .-name
 
 /*
- * Certain SoCs have an alignment requiremnt for the CPU reset vector.
+ * Certain SoCs have an alignment requirement for the CPU reset vector.
  * Align to a 64 byte typical cacheline for now.
  */
 #define CPU_RESET_ENTRY(name) ENTRY_WITH_ALIGN(name, 6)

src/arch/riscv/fit_payload.c

@@ -7,7 +7,7 @@
 #include <fit.h>
 #include <endian.h>
 
-/* Implements a Berkley Boot Loader (BBL) compatible payload loading */
+/* Implements a Berkeley Boot Loader (BBL) compatible payload loading */
 
 #define MAX_KERNEL_SIZE (64*MiB)
 

src/arch/riscv/opensbi.c

@@ -2,7 +2,7 @@
 
 #include <sbi/fw_dynamic.h>
 #include <arch/boot.h>
-/* DO NOT INLCUDE COREBOOT HEADERS HERE */
+/* DO NOT INCLUDE COREBOOT HEADERS HERE */
 
 void run_opensbi(const int hart_id,
 		 const void *fdt,

src/arch/x86/c_start.S

@@ -217,7 +217,7 @@ SetCodeSelector:
 	# use iret to jump to a 64-bit offset in a new code segment
 	# iret will pop cs:rip, flags, then ss:rsp
 	mov	%ss, %ax	# need to push ss..
-	push	%rax		# push ss instuction not valid in x64 mode,
+	push	%rax		# push ss instruction not valid in x64 mode,
 				# so use ax
 	push	%rsp
 	pushfq

src/commonlib/bsd/include/commonlib/bsd/compiler.h

@@ -36,7 +36,7 @@
 #endif
 
 /* This evaluates to the type of the first expression, unless that is constant
-   in which case it evalutates to the type of the second. This is useful when
+   in which case it evaluates to the type of the second. This is useful when
    assigning macro parameters to temporary variables, because that would
    normally circumvent the special loosened type promotion rules for integer
    literals. By using this macro, the promotion can happen at the time the

src/commonlib/include/commonlib/iobuf.h

@@ -81,7 +81,7 @@ int ibuf_split(const struct ibuf *src, struct ibuf *a, struct ibuf *b,
 /* Out-of-band drain of ibuf by returning pointer to data of specified size. */
 const void *ibuf_oob_drain(struct ibuf *ib, size_t sz);
 
-/* Read arbitray data from input buffer. */
+/* Read arbitrary data from input buffer. */
 int ibuf_read(struct ibuf *ib, void *data, size_t sz);
 
 /* Read big endian fixed size values. */
@@ -125,7 +125,7 @@ int obuf_split(const struct obuf *src, struct obuf *a, struct obuf *b,
 /* Fill the buffer out-of-band. The size is accounted for. */
 void *obuf_oob_fill(struct obuf *ob, size_t sz);
 
-/* Write arbitray data to output buffer. */
+/* Write arbitrary data to output buffer. */
 int obuf_write(struct obuf *ob, const void *data, size_t sz);
 
 /* Write big endian fixed size values. */

src/console/Kconfig

@@ -193,7 +193,7 @@ config CONSOLE_NE2K
 	help
 	  Send coreboot debug output to a Ethernet console, it works
 	  same way as Linux netconsole, packets are received to UDP
-	  port 6666 on IP/MAC specified with options bellow.
+	  port 6666 on IP/MAC specified with options below.
 	  Use following netcat command: nc -u -l -p 6666
 
 config CONSOLE_NE2K_DST_MAC

src/cpu/x86/64bit/exit32.inc

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
- * For droping from long mode to protected mode.
+ * For dropping from long mode to protected mode.
  *
  * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2",
  * Document 24593-Rev. 3.31-July 2019 Chapter 5.3
@@ -47,7 +47,7 @@ SetCodeSelector32:
 
 	# use iret to jump to a 32-bit offset in a new code segment
 	# iret will pop cs:rip, flags, then ss:rsp
-	mov	%ss, %ax	# need to push ss, but push ss instuction
+	mov	%ss, %ax	# need to push ss, but push ss instruction
 	push	%rax		# not valid in x64 mode, so use ax
 	push	%rdx		# the rsp to load
 	pushfq			# push rflags

src/cpu/x86/pae/pgtbl.c

@@ -104,7 +104,7 @@ void paging_disable_pae(void)
  * Use PAE to map a page and then memset it with the pattern specified.
  * In order to use PAE pagetables for virtual addressing are set up and reloaded
  * on a 2MiB boundary. After the function is done, virtual addressing mode is
- * disabled again. The PAT are set to all cachable, but MTRRs still apply.
+ * disabled again. The PAT are set to all cacheable, but MTRRs still apply.
  *
  * Requires a scratch memory for pagetables and a virtual address for
  * non identity mapped memory.
@@ -124,7 +124,7 @@ void paging_disable_pae(void)
  *                  Content at physical address isn't preserved.
  * @param length    The length of the memory segment to memset
  * @param dest      Physical memory address to memset
- * @param pat       The pattern to write to the pyhsical memory
+ * @param pat       The pattern to write to the physical memory
  * @return 0 on success, 1 on error
  */
 int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,

src/cpu/x86/sipi_vector.S

@@ -57,7 +57,7 @@ _start:
 	movw	%cs, %ax
 	movw	%ax, %ds
 
-	/* The gdtaddr needs to be releative to the data segment in order
+	/* The gdtaddr needs to be relative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
 	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx

src/device/Kconfig

@@ -166,7 +166,7 @@ config ALWAYS_RUN_OPROM
 	def_bool n
 	depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM
 	help
-	  Always uncondtionally run the option regardless of other
+	  Always unconditionally run the option regardless of other
 	  policies.
 
 config ON_DEVICE_ROM_LOAD

src/device/azalia_device.c

@@ -289,7 +289,7 @@ void azalia_audio_init(struct device *dev)
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the azalia_audio get's a bar above 4G.
+	// NOTE this will break as soon as the azalia_audio gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);

src/device/dram/ddr4.c

@@ -205,7 +205,7 @@ int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
 
 	/* Verify CRC of blocks that have them, do not step over 'used' length */
 	for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) {
-		/* this block is not checksumed */
+		/* this block is not checksummed */
 		if (spd_blocks[i].crc_start == 0)
 			continue;
 		/* we shouldn't have this block */

src/device/oprom/include/x86emu/regs.h

@@ -54,7 +54,7 @@
  * EAX & 0xff  === AL
  * EAX & 0xffff == AX
  *
- * etc.  The result is that alot of the calculations can then be
+ * etc.  The result is that a lot of the calculations can then be
  * done using the native instruction set fully.
  */
 

src/device/oprom/x86emu/LICENSE

@@ -1,7 +1,7 @@
                          License information
                          -------------------
 
-The x86emu library is under a BSD style license, comaptible
+The x86emu library is under a BSD style license, compatible
 with the XFree86 and X licenses used by XFree86. The
 original x86emu libraries were under the GNU General Public
 License. Due to license incompatibilities between the GPL

src/device/oprom/x86emu/prim_ops.c

@@ -2458,7 +2458,7 @@ void x86emu_cpuid(void)
     switch (feature) {
     case 0:
         /* Regardless if we have real data from the hardware, the emulator
-         * will only support upto feature 1, which we set in register EAX.
+         * will only support up to feature 1, which we set in register EAX.
          * Registers EBX:EDX:ECX contain a string identifying the CPU.
          */
         M.x86.R_EAX = 1;

src/device/pci_early.c

@@ -104,7 +104,7 @@ void pci_early_bridge_init(void)
 }
 
 /* FIXME: A lot of issues using the following, please avoid.
- * Assumes 256 PCI busses, scans them all even when PCI bridges are still
+ * Assumes 256 PCI buses, scans them all even when PCI bridges are still
  * disabled. Probes all functions even if 0 is not present.
  */
 pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)

src/device/pnp_device.c

@@ -238,7 +238,7 @@ static void pnp_get_ioresource(struct device *dev, u8 index, u16 mask)
 	resource->limit = (1 << (bit + 1)) - 1;
 
 	/* The block of ones in the mask is expected to be continuous.
-	   If there is any zero inbetween the block of ones, it is ignored
+	   If there is any zero in between the block of ones, it is ignored
 	   in the calculation of the resource size and limit. */
 	if (mask != (resource->limit ^ (resource->size - 1)))
 		printk(BIOS_WARNING,

src/device/resource_allocator_v4.c

@@ -637,7 +637,7 @@ static void allocate_domain_resources(const struct device *domain)
  * order to accomplish best fit for the resources, a list of ranges is maintained by each
  * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since
  * they are allocated space from the same window, the resource allocator at the domain level
- * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the
+ * ensures that the biggest requirement is selected independent of the prefetch type. Once the
  * resource allocation for all immediate downstream devices is complete at the domain level,
  * resource allocator walks down the subtree for each downstream bridge to continue the
  * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and

src/drivers/amd/agesa/cache_as_ram.S

@@ -5,7 +5,7 @@
  *
  * $Workfile:: cache_as_ram.S
  *
- * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier
+ * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler
  *
  ******************************************************************************
  */

src/drivers/crb/tpm.c

@@ -6,7 +6,7 @@
  *
  * TPM starts in IDLE Mode
  *
- *   IDLE  --> READY --> Command Receiption
+ *   IDLE  --> READY --> Command Reception
  *    ^	                        |
  *    |	                        v
       -- Cmd Complete <-- Command Execution

src/drivers/generic/gpio_keys/chip.h

@@ -81,7 +81,7 @@ struct drivers_generic_gpio_keys_config {
 	struct acpi_gpio gpio;
 	/* Is this a polled GPIO button? - Optional */
 	bool is_polled;
-	/* Poll inverval - Mandatory only if GPIO is polled. */
+	/* Poll interval - Mandatory only if GPIO is polled. */
 	uint32_t poll_interval;
 	/* Details about the key - Mandatory */
 	struct key_info key;

src/drivers/i2c/lm96000/chip.h

@@ -90,7 +90,7 @@ struct lm96000_temp_zone {
 	enum {
 		/* turn fan off below `low_temp - hysteresis` */
 		LM96000_LOW_TEMP_OFF = 0,
-		/* keep PWM at mininum duty cycle */
+		/* keep PWM at minimum duty cycle */
 		LM96000_LOW_TEMP_MIN = 1,
 	} min_off;
 	u8 hysteresis;

src/drivers/i2c/nct7802y/chip.h

@@ -37,7 +37,7 @@ enum nct7802y_fan_mode {
 
 enum nct7802y_fan_smartmode {
 	SMART_FAN_DUTY = 0,	/* Target values given in duty cycle %. */
-	SMART_FAN_RPM,		/* Target valuse given in RPM. */
+	SMART_FAN_RPM,		/* Target values given in RPM. */
 };
 
 enum nct7802y_fan_speed {

src/drivers/i2c/tpm/cr50.c

@@ -3,7 +3,7 @@
 /* Based on Linux Kernel TPM driver */
 
 /*
- * cr50 is a TPM 2.0 capable device that requries special
+ * cr50 is a TPM 2.0 capable device that requires special
  * handling for the I2C interface.
  *
  * - Use an interrupt for transaction status instead of hardcoded delays

src/drivers/i2c/tpm/tpm.c

@@ -35,7 +35,7 @@
 
 /* max. number of iterations after I2C NAK for 'long' commands
  * we need this especially for sending TPM_READY, since the cleanup after the
- * transtion to the ready state may take some time, but it is unpredictable
+ * transition to the ready state may take some time, but it is unpredictable
  * how long it will take.
  */
 #define MAX_COUNT_LONG 50

src/drivers/i2c/ww_ring/ww_ring_programs.c

@@ -91,7 +91,7 @@ static const TiLp55231Program solid_000000_program = {
  *
  * When solid patterns are deployed with instanteneous color intensity
  * changes, all three LEDs can be controlled by one engine in sequential
- * accesses. But the controllers still neeed to be synchronized.
+ * accesses. But the controllers still need to be synchronized.
  *
  * The maximum timer duration of lp55231 is .48 seconds. To achieve longer
  * blinking intervals the loops delays are deployed. Only the first controller

src/drivers/i2c/ww_ring/ww_ring_programs.h

@@ -21,7 +21,7 @@
 #include <stdint.h>
 #include "drivers/i2c/ww_ring/ww_ring.h"
 
-/* There are threee independent engines/cores in the controller. */
+/* There are three independent engines/cores in the controller. */
 #define LP55231_NUM_OF_ENGINES 3
 
 /* Number of lp55321 controllers on the ring */
@@ -29,7 +29,7 @@
 
 /*
  * Structure to describe an lp55231 program: pointer to the text of the
- * program, its size and load address (load addr + size sould not exceed
+ * program, its size and load address (load addr + size should not exceed
  * LP55231_MAX_PROG_SIZE), and start addresses for all of the three
  * engines.
  */

src/drivers/ipmi/ipmi_fru.c

@@ -525,7 +525,7 @@ void print_fru_areas(struct fru_info_str *fru_info_str)
 	if (prod_info.product_name != NULL)
 		printk(BIOS_DEBUG, "product name: %s\n", prod_info.product_name);
 	if (prod_info.product_partnumber != NULL)
-		printk(BIOS_DEBUG, "product part numer: %s\n", prod_info.product_partnumber);
+		printk(BIOS_DEBUG, "product part number: %s\n", prod_info.product_partnumber);
 	if (prod_info.product_version != NULL)
 		printk(BIOS_DEBUG, "product version: %s\n", prod_info.product_version);
 	if (prod_info.serial_number != NULL)

src/drivers/ipmi/supermicro_oem.c

@@ -26,7 +26,7 @@ static void set_coreboot_ver(const uint16_t kcs_port)
 	int ret;
 	size_t i;
 
-	/* Only 8 charactars are visible in UI. Cut of on first dash */
+	/* Only 8 characters are visible in UI. Cut of on first dash */
 	for (i = 0; i < 15; i++) {
 		if (coreboot_ver[i] == '-')
 			break;

src/drivers/net/Kconfig

@@ -33,7 +33,7 @@ config RT8168_SET_LED_MODE
 	select REALTEK_8168_RESET
 	help
 	  This is to set a customized LED mode to distinguish 10/100/1000
-	  link and speed status with limited LEDs avaiable on a board.
+	  link and speed status with limited LEDs available on a board.
 	  Please refer to RTL811x datasheet section 7.2 Customizable LED
 	  Configuration for details. With this flag enabled, the
 	  customized_leds variable will be read from devicetree setting.

src/drivers/net/atl1e.c

@@ -127,7 +127,7 @@ static void atl1e_init(struct device *dev)
 
 	/* Check if the base is invalid */
 	if (!mem_base) {
-		printk(BIOS_ERR, "atl1e: Error cant find MEM resource\n");
+		printk(BIOS_ERR, "atl1e: Error can't find MEM resource\n");
 		return;
 	}
 	/* Enable but do not set bus master */

src/drivers/net/r8168.c

@@ -280,7 +280,7 @@ static void r8168_init(struct device *dev)
 
 	/* Check if the base is invalid */
 	if (!io_base) {
-		printk(BIOS_ERR, "r8168: Error cant find IO resource\n");
+		printk(BIOS_ERR, "r8168: Error can't find IO resource\n");
 		return;
 	}
 	/* Enable but do not set bus master */

src/drivers/spi/spi_sdcard.c

@@ -683,7 +683,7 @@ int spi_sdcard_single_write(const struct spi_sdcard *card,
 	spi_sdcard_sendbyte(card, 0xff & (c >> 8));
 	spi_sdcard_sendbyte(card, 0xff & (c >> 0));
 
-	/* recevie and verify data response token */
+	/* receive and verify data response token */
 	c = spi_sdcard_recvbyte(card);
 	if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) {
 		spi_sdcard_disable_cs(card);
@@ -742,7 +742,7 @@ int spi_sdcard_multiple_write(const struct spi_sdcard *card,
 		spi_sdcard_sendbyte(card, 0xff & (c >> 8));
 		spi_sdcard_sendbyte(card, 0xff & (c >> 0));
 
-		/* recevie and verify data response token */
+		/* receive and verify data response token */
 		c = spi_sdcard_recvbyte(card);
 		if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED)
 			break;

src/drivers/spi/tpm/tpm.c

@@ -3,7 +3,7 @@
  *
  * It assumes that the required SPI interface has been initialized before the
  * driver is started. A 'sruct spi_slave' pointer passed at initialization is
- * used to direct traffic to the correct SPI interface. This dirver does not
+ * used to direct traffic to the correct SPI interface. This driver does not
  * provide a way to instantiate multiple TPM devices. Also, to keep things
  * simple, the driver unconditionally uses of TPM locality zero.
  *
@@ -159,7 +159,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
 
 	/*
 	 * The first byte of the frame header encodes the transaction type
-	 * (read or write) and transfer size (set to lentgh - 1), limited to
+	 * (read or write) and transfer size (set to length - 1), limited to
 	 * 64 bytes.
 	 */
 	header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1);
@@ -188,7 +188,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
 	 * the last clock of the byte) is set to 1.
 	 *
 	 * Due to some SPI controllers' shortcomings (Rockchip comes to
-	 * mind...) we trasmit the 4 byte header without checking the byte
+	 * mind...) we transmit the 4 byte header without checking the byte
 	 * transmitted by the TPM during the transaction's last byte.
 	 *
 	 * We know that cr50 is guaranteed to set the flow control bit to 0

src/ec/compal/ene932/acpi/ec.asl

@@ -118,7 +118,7 @@ Device (EC0)
 		SWTO, 1,        // SW Throttling (1=Active)             ; AEh.6
 		TTHR, 1,        // HW (THRM#) Throttling (1=Active)     ; AEh.7
 		TTHM, 1,        // TS_THERMAL(1:Throttling for thermal) ; AFh.0
-		THTL, 1,        // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1
+		THTL, 1,        // THROTTLING(1:Ctrl H/W throttling act); AFh.1
 		, 2,            // Reserved                             ; AFh.2-3
 		NPST, 4,        // Number of P-State level              ; AFh.4-7
 		CTMP, 8,        // Current CPU Temperature              ; B0h

src/ec/google/chromeec/ec.h

@@ -161,7 +161,7 @@ int crosec_command_proto(struct chromeec_command *cec_command,
 			 crosec_io_t crosec_io, void *context);
 
 /**
- * Performs light verification of the EC<->AP communcation channel.
+ * Performs light verification of the EC<->AP communication channel.
  *
  * @return		0 on success, -1 on error
  */
@@ -330,7 +330,7 @@ struct usb_pd_port_caps {
  * Get role-based capabilities for a USB-PD port
  *
  * @param port			Which port to get information about
- * @param *power_role_cap	The power-role capabillity of the port
+ * @param *power_role_cap	The power-role capability of the port
  * @param *try_power_role_cap	The Try-power-role capability of the port
  * @param *data_role_cap	The data role capability of the port
  * @param *port_location	Location of the port on the device

src/ec/google/chromeec/ec_commands.h

@@ -2856,7 +2856,7 @@ struct ec_params_motion_sense {
 		 */
 		struct __ec_todo_unpacked {
 			/* Data to set or EC_MOTION_SENSE_NO_VALUE to read.
-			 * kb_wake_angle: angle to wakup AP.
+			 * kb_wake_angle: angle to wake up AP.
 			 */
 			int16_t data;
 		} kb_wake_angle;

src/ec/google/wilco/commands.h

@@ -10,7 +10,7 @@ enum {
 	KB_POWER_SMI = 0x04,
 	/* Read but do not clear power state information */
 	KB_POWER_STATUS = 0x05,
-	/* Inform the EC aboout the reason host is turning off */
+	/* Inform the EC about the reason host is turning off */
 	KB_POWER_OFF = 0x08,
 	/* Control wireless radios */
 	KB_RADIO_CONTROL = 0x2b,

src/ec/quanta/ene_kb3940q/acpi/ec.asl

@@ -75,7 +75,7 @@ Device (EC0)
 		KBID, 1,        // 0=EN KBD, 1=JP KBD                   ; 80h.1
 		    , 6,        // Reserved                             ; 80h.2-7
 		NPST, 8,        // Number of P-State level              ; 81h
-		MPST, 8,        // Maxumum P-State                      ; 82h
+		MPST, 8,        // Maximum P-State                      ; 82h
 		KWAK, 1,        // Keyboard WAKE(0=Disable,1=Enable)    ; 83h.0
 		TWAK, 1,        // TouchPad WAKE(0=Disable,1=Enable)    ; 83h.1
 		    , 1,        // Reserved                             ; 83h.2

src/ec/quanta/it8518/acpi/battery.asl

@@ -23,7 +23,7 @@ Device (BATX)
 		0,            //  0: Power Unit
 		0xFFFFFFFF,   //  1: Design Capacity
 		0xFFFFFFFF,   //  2: Last Full Charge Capacity
-		1,            //  3: Battery Technology(Rechargable)
+		1,            //  3: Battery Technology(Rechargeable)
 		10800,        //  4: Design Voltage 10.8V
 		0,            //  5: Design capacity of warning
 		0,            //  6: Design capacity of low

src/ec/quanta/it8518/acpi/ec.asl

@@ -444,7 +444,7 @@ Device (EC0)
 		MBTH, 4,        //   bit 3-0: battery 0 highest level
 		SBTH, 4,        //   bit 7-4: battery 1 highest level
 		                //   note: if highest level is 0 or 0xF, it means not defined
-		                //         (in this case, use default hightest level, it is 6)
+		                //         (in this case, use default highest level, it is 6)
 
 		Offset(0xEF),   // [EC Function Specification Major Version]
 		Offset(0xF0),   // [Build ID]~ offset:0F7h

src/include/acpi/acpi.h

@@ -1267,7 +1267,7 @@ void acpi_create_slit(acpi_slit_t *slit,
  * proximimity domain for the memory.
  */
 int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory);
-/* Create Heterogenous Memory Attribute Table */
+/* Create Heterogeneous Memory Attribute Table */
 void acpi_create_hmat(acpi_hmat_t *hmat,
 		      unsigned long (*acpi_fill_hmat)(unsigned long current));
 

src/include/cpu/x86/save_state.h

@@ -26,7 +26,7 @@ struct smm_save_state_ops {
 
 /* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */
 int get_apmc_node(u8 cmd);
-/* Return -1 on failure, 0 on succes.
+/* Return -1 on failure, 0 on success.
    Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */
 int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length);
 int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length);

src/include/device/i2c_simple.h

@@ -35,7 +35,7 @@ int i2c_write_field(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data,
 
 /*
  * software_i2c is supposed to be a debug feature. It's usually not compiled in,
- * but when it is it can be dynamically enabled at runtime for certain busses.
+ * but when it is it can be dynamically enabled at runtime for certain buses.
  * Need this ugly stub to arbitrate since I2C device drivers hardcode
  * 'i2c_transfer()' as their entry point.
  */

src/lib/device_tree.c

@@ -758,7 +758,7 @@ struct device_tree_node *dt_find_compat(struct device_tree_node *parent,
 }
 
 /*
- * Find the next compatible child of a given parent. All children upto the
+ * Find the next compatible child of a given parent. All children up to the
  * child passed in by caller are ignored. If child is NULL, it considers all the
  * children to find the first child which is compatible.
  *

src/lib/edid.c

@@ -433,7 +433,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
 
 			/*
 			 * Slightly weird to return a global, but I've never
-			 * seen any EDID block wth two range descriptors, so
+			 * seen any EDID block with two range descriptors, so
 			 * it's harmless.
 			 */
 			return 1;
@@ -481,7 +481,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
 	  We have no samples between those values, so put a
 	  threshold at 95000 kHz. If we get anything over
 	  95000 kHz with single channel, we can make this
-	  more sofisticated but it's currently not needed.
+	  more sophisticated but it's currently not needed.
 	 */
 	out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000);
 	extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4));
@@ -1094,7 +1094,7 @@ int set_display_mode(struct edid *edid, enum edid_modes mode)
 }
 
 /*
- * Given a raw edid bloc, decode it into a form
+ * Given a raw edid block, decode it into a form
  * that other parts of coreboot can use -- mainly
  * graphics bringup functions. The raw block is
  * required to be 128 bytes long, per the standard,

src/lib/nhlt.c

@@ -126,7 +126,7 @@ struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endp,
 	wave->channel_mask = speaker_mask;
 	memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format));
 
-	/* Calculate the dervied fields. */
+	/* Calculate the derived fields. */
 	wave->block_align = wave->num_channels * wave->bits_per_sample / 8;
 	wave->bytes_per_second = wave->block_align * wave->samples_per_second;
 

src/lib/region_file.c

@@ -9,7 +9,7 @@
  * A region file provides generic support for appending new data
  * within a storage region. The book keeping is tracked in metadata
  * blocks where an offset pointer points to the last byte of a newly
- * allocated byte sequence. Thus, by taking 2 block offets one can
+ * allocated byte sequence. Thus, by taking 2 block offsets one can
  * determine start and size of the latest update. The data does not
  * have to be the same consistent size, but the data size has be small
  * enough to fit a metadata block and one data write within the region.