soc/intel/mtl: Enable IOE_PMC support

IOE_PMC support was not enabled on Meteor Lake platforms. This patch
adds the bare minimum hooks to initialize and allocate a memory region
for IOE operations. Additionally, this patch moves those IOE operations
to a newly included IOE-specific file, Previously, PMC was responsible
for these operations.

BUG=b:287419766
TEST=build and verified on google/rex.

Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dinesh Gehlot 2023-08-18 10:04:53 +05:30 committed by Martin L Roth
parent 2c40670fad
commit 095043fcca
5 changed files with 30 additions and 3 deletions

View File

@ -32,6 +32,7 @@ ramstage-y += acpi.c
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
ramstage-y += ioe_pmc.c
ramstage-y += elog.c
ramstage-y += espi.c
ramstage-y += finalize.c

View File

@ -231,6 +231,9 @@ static void soc_enable(struct device *dev)
else if (dev->path.type == DEVICE_PATH_PCI &&
dev->path.pci.devfn == PCI_DEVFN_PMC)
dev->ops = &pmc_ops;
else if (dev->path.type == DEVICE_PATH_PCI &&
dev->path.pci.devfn == PCI_DEVFN_IOE_PMC)
dev->ops = &ioe_pmc_ops;
else if (dev->path.type == DEVICE_PATH_PCI &&
dev->path.pci.devfn == PCI_DEVFN_P2SB)
dev->ops = &soc_p2sb_ops;

View File

@ -5,6 +5,7 @@
#include <device/device.h>
extern struct device_operations pmc_ops;
extern struct device_operations ioe_pmc_ops;
/* PCI Configuration Space (D31:F2): PMC */
#define PWRMBASE 0x10

View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <intelblocks/pmc.h>
#include <soc/iomap.h>
#include <soc/pm.h>
static void ioe_pmc_read_resources(struct device *dev)
{
/* Add the fixed MMIO resource */
mmio_range(dev, PWRMBASE, IOE_PWRM_BASE_ADDRESS, IOE_PWRM_BASE_SIZE);
}
static void ioe_pmc_init(struct device *dev)
{
if (!CONFIG(USE_PM_ACPI_TIMER))
setbits8(ioe_pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
}
struct device_operations ioe_pmc_ops = {
.read_resources = ioe_pmc_read_resources,
.set_resources = noop_set_resources,
.init = ioe_pmc_init,
};

View File

@ -156,10 +156,8 @@ static void soc_pmc_init(struct device *dev)
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*/
if (!CONFIG(USE_PM_ACPI_TIMER)) {
if (!CONFIG(USE_PM_ACPI_TIMER))
setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
setbits8(ioe_pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
}
}
static void pm1_enable_pwrbtn_smi(void *unused)