soc/intel/mtl: Enable IOE_PMC support
IOE_PMC support was not enabled on Meteor Lake platforms. This patch adds the bare minimum hooks to initialize and allocate a memory region for IOE operations. Additionally, this patch moves those IOE operations to a newly included IOE-specific file, Previously, PMC was responsible for these operations. BUG=b:287419766 TEST=build and verified on google/rex. Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -32,6 +32,7 @@ ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
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ramstage-y += ioe_pmc.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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@ -231,6 +231,9 @@ static void soc_enable(struct device *dev)
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else if (dev->path.type == DEVICE_PATH_PCI &&
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dev->path.pci.devfn == PCI_DEVFN_PMC)
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dev->ops = &pmc_ops;
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else if (dev->path.type == DEVICE_PATH_PCI &&
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dev->path.pci.devfn == PCI_DEVFN_IOE_PMC)
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dev->ops = &ioe_pmc_ops;
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else if (dev->path.type == DEVICE_PATH_PCI &&
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dev->path.pci.devfn == PCI_DEVFN_P2SB)
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dev->ops = &soc_p2sb_ops;
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@ -5,6 +5,7 @@
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#include <device/device.h>
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extern struct device_operations pmc_ops;
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extern struct device_operations ioe_pmc_ops;
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/* PCI Configuration Space (D31:F2): PMC */
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#define PWRMBASE 0x10
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <intelblocks/pmc.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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static void ioe_pmc_read_resources(struct device *dev)
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{
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/* Add the fixed MMIO resource */
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mmio_range(dev, PWRMBASE, IOE_PWRM_BASE_ADDRESS, IOE_PWRM_BASE_SIZE);
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}
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static void ioe_pmc_init(struct device *dev)
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{
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if (!CONFIG(USE_PM_ACPI_TIMER))
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setbits8(ioe_pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
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}
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struct device_operations ioe_pmc_ops = {
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.read_resources = ioe_pmc_read_resources,
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.set_resources = noop_set_resources,
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.init = ioe_pmc_init,
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};
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@ -156,10 +156,8 @@ static void soc_pmc_init(struct device *dev)
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*/
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if (!CONFIG(USE_PM_ACPI_TIMER)) {
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if (!CONFIG(USE_PM_ACPI_TIMER))
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setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
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setbits8(ioe_pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
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}
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}
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static void pm1_enable_pwrbtn_smi(void *unused)
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