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soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current values

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The Intel Power and Performance (PnP) team requested to update the
following:
- TDC settings for RPL-U 15W variant should be 22A.
- TDC settings for RPL-P 28W variant should be 33A.

BUG=b:275694022
BRANCH=firmware-brya-14505.B
TEST=PnP validated performance impact with these settings on both
     RPL-U 15W and RPL-P 28W

Change-Id: I1141414785a990b975e32ebc03e490b83082aab7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2023-03-27 11:57:41 -07:00 committed by Felix Held
parent 537213a40e
commit 0973c32c5d
1 changed files with 8 additions and 8 deletions
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16
src/soc/intel/alderlake/vr_config.c
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@ -80,13 +80,13 @@
* + +-----------+-------+-------+---------+-------------+----------+
* | | GT | 3.2 | 3.2 | 55 | 86 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 54 | 28000 |
* | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 33 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
* | | GT | 3.2 | 3.2 | 55 | 54 | 28000 |
* | | GT | 3.2 | 3.2 | 55 | 33 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
* | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 41 | 28000 |
* | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 22 | 28000 |
* + +-----------+-------+-------+---------+-------------+----------+
* | | GT | 3.2 | 3.2 | 40 | 41 | 28000 |
* | | GT | 3.2 | 3.2 | 40 | 22 | 28000 |
* +----------------+-----------+-------+-------+---------+-------------+----------+
*/
@ -245,10 +245,10 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) },
{ PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) },
{ PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
{ PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
{ PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
{ PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
{ PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
{ PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
{ PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) },
{ PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) },