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nb/intel/sandybridge: Use IOSAV_BYTE_SERROR_C_ch macro 

This changes the binary because the operations get reordered, but it is
otherwise equivalent.

Change-Id: I362187b2889e6f7a68bf752a23c1279cebf961f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons 2020-03-22 12:55:32 +01:00 committed by Patrick Georgi
parent 0c3936e41b
commit 098240eb4f
1 changed files with 3 additions and 3 deletions
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6
src/northbridge/intel/sandybridge/raminit_common.c
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@ -2626,7 +2626,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr
}
/* FIXME: This register only exists on Ivy Bridge */
raw_stats[edge] = MCHBAR32(0x436c + channel * 0x400);
raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel));
}
FOR_ALL_LANES {
@ -2797,8 +2797,8 @@ int discover_timC_write(ramctr_timing *ctrl)
test_timC_write (ctrl, channel, slotrank);
/* FIXME: Another IVB-only register! */
raw_stats[timC] =
MCHBAR32(0x436c + channel * 0x400);
raw_stats[timC] = MCHBAR32(
IOSAV_BYTE_SERROR_C_ch(channel));
}
FOR_ALL_LANES {
struct run rn;