soc/intel/cannonlake: Add PCI dev macros and IDs
Change-Id: I287404f1615c6c0b441dd1b98a40e79919920a02 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Andrey Petrov
Aaron Durbin
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CANNONLAKE_PCI_DEVS_H_
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#define _SOC_CANNONLAKE_PCI_DEVS_H_
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#include <device/pci_def.h>
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#include <rules.h>
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#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#include <device/pci_def.h>
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#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
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#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
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#else
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#include <arch/io.h>
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#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
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#endif
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/* System Agent Devices */
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#define SA_DEV_SLOT_ROOT 0x00
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#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
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#define SA_DEV_ROOT _SA_DEV(ROOT)
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#define SA_DEV_SLOT_IGD 0x02
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#define SA_DEVFN_IGD _SA_DEVFN(IGD)
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#define SA_DEV_IGD _SA_DEV(IGD)
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#define SA_DEV_SLOT_DSP 0x04
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#define SA_DEVFN_DSP _SA_DEVFN(DSP)
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#define SA_DEV_DSP _SA_DEV(DSP)
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/* PCH Devices */
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#define PCH_DEV_SLOT_THERMAL 0x12
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#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)
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#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5)
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#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6)
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#define PCH_DEV_SLOT_ISH 0x13
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#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)
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#define PCH_DEV_SLOT_XHCI 0x14
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#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
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#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1)
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#define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3)
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#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1)
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#define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3)
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#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)
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#define PCH_DEV_SLOT_SIO1 0x15
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#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0)
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#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1)
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#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2)
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#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3)
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#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0)
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#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1)
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#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2)
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#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3)
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#define PCH_DEV_SLOT_CSE 0x16
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#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
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#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
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#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2)
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#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3)
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#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
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#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5)
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#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
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#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
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#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2)
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#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3)
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#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
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#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5)
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#define PCH_DEV_SLOT_SATA 0x17
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#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0)
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#define PCH_DEV_SATA _PCH_DEV(SATA, 0)
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#define PCH_DEV_SLOT_SIO2 0x19
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#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0)
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#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1)
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#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2)
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#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0)
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#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1)
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#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2)
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#define PCH_DEV_SLOT_STORAGE 0x1A
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#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)
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#define PCH_DEV_SLOT_PCIE 0x1c
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#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0)
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#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1)
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#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2)
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#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3)
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#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4)
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#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5)
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#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6)
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#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7)
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#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0)
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#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1)
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#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2)
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#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)
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#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)
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#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)
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#define PCH_DEV_SLOT_PCIE_1 0x1d
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#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)
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#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
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#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
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#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
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#define PCH_DEV_SLOT_SIO3 0x1e
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#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)
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#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1)
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#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2)
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#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3)
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#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0)
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#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1)
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
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#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
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#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3)
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#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
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#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
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#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6)
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#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7)
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#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
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#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
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#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
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#define PCH_DEV_HDA _PCH_DEV(LPC, 3)
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#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
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#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
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#define PCH_DEV_GBE _PCH_DEV(LPC, 6)
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static inline int spi_devfn_to_bus(unsigned int devfn)
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{
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switch (devfn) {
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case PCH_DEVFN_SPI: return 0;
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case PCH_DEVFN_GSPI0: return 1;
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case PCH_DEVFN_GSPI1: return 2;
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}
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return -1;
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}
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static inline int spi_bus_to_devfn(unsigned int bus)
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{
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switch (bus) {
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case 0: return PCH_DEVFN_SPI;
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case 1: return PCH_DEVFN_GSPI0;
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case 2: return PCH_DEVFN_GSPI1;
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}
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return -1;
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}
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#endif
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