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soc/intel/cannonlake/bootblock: Fix FSP CAR 

Fix FSP CAR on platforms that have ROM_SIZE of 32MiB.
CodeRegionSize must be smaller than or equal to 16MiB
to not overlap with LAPIC or the CAR area at 0xfef00000.

Tested on Intel CFL, the new code allows to boot using FSP-T.

Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph 2020-03-13 07:48:55 +01:00 committed by Patrick Georgi
parent d991bf1fb4
commit 09a106907e
1 changed files with 6 additions and 3 deletions
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9
src/soc/intel/cannonlake/bootblock/bootblock.c
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@ -2,6 +2,7 @@
/* This file is part of the coreboot project. */
#include <bootblock_common.h>
#include <cpu/x86/mtrr.h>
#include <intelblocks/gspi.h>
#include <intelblocks/uart.h>
#include <soc/bootblock.h>
@ -28,12 +29,14 @@ const FSPT_UPD temp_ram_init_params = {
* even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to
* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize.
*
* Note: CodeRegionSize must be smaller than or equal to 16MiB to not
* overlap with LAPIC or the CAR area at 0xfef00000.
*/
.MicrocodeRegionBase = 0,
.MicrocodeRegionSize = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
.CodeRegionBase = (uint32_t)0x100000000ULL - CACHE_ROM_SIZE,
.CodeRegionSize = (uint32_t)CACHE_ROM_SIZE,
},
};
#endif