mb/asrock/h81m-hds: Move GPIO header to a linked C file

Using a linked C file is the standard approach for GPIO settings.

Change-Id: I6a5ca65bc1553bd382589d67379eafd03dc0b0a3
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/mainboard/asrock/h81m-hds/Makefile.inc

@@ -14,4 +14,5 @@
 ## GNU General Public License for more details.
 ##
 
+romstage-y += gpio.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/asrock/h81m-hds/gpio.c

@@ -14,9 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#ifndef ASROCK_H81M_HDS_GPIO_H
-#define ASROCK_H81M_HDS_GPIO_H
-
 #include <southbridge/intel/common/gpio.h>
 
 static const struct pch_gpio_set1 pch_gpio_set1_mode = {
@@ -164,5 +161,3 @@ const struct pch_gpio_map mainboard_gpio_map = {
 		.reset		= &pch_gpio_set3_reset,
 	},
 };
-
-#endif /* ASROCK_H81M_HDS_GPIO_H */

src/mainboard/asrock/h81m-hds/romstage.c

@@ -20,10 +20,10 @@
 #include <cpu/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6776/nct6776.h>
-#include "gpio.h"
 
 static const struct rcba_config_instruction rcba_config[] = {
 	RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),