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cpu/x86/mp_init: Support both xapic and x2apic with common code 

Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT,
specifically for (obsolete) Init Level De-assert.

Level LAPIC_INT_ASSERT is required to be set for all other delivery
modes other than LAPIC_DM_INIT.

This reverts the two above changes that X2APIC mode support introduced
to the IPI for LAPIC_DM_SMI.

Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2021-05-21 09:32:45 +02:00 committed by Kyösti Mälkki
parent a5061f8f57
commit 09a6d633ae
1 changed files with 10 additions and 30 deletions
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40
src/cpu/x86/mp_init.c
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@ -435,27 +435,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count); printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count);
if (is_x2apic_mode()) { int x2apic_mode = is_x2apic_mode();
x2apic_send_ipi(LAPIC_DM_INIT | LAPIC_INT_LEVELTRIG | printk(BIOS_DEBUG, "Starting CPUs in %s mode\n", x2apic_mode ? "x2apic" : "xapic");
LAPIC_INT_ASSERT | LAPIC_DEST_ALLBUT, 0);
mdelay(10);
x2apic_send_ipi(LAPIC_DM_STARTUP | LAPIC_INT_LEVELTRIG |
LAPIC_DEST_ALLBUT | sipi_vector, 0);
/* Wait for CPUs to check in up to 200 us. */
wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */);
x2apic_send_ipi(LAPIC_DM_STARTUP | LAPIC_INT_LEVELTRIG |
LAPIC_DEST_ALLBUT | sipi_vector, 0);
/* Wait for CPUs to check in. */
if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) {
printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n",
atomic_read(num_aps), ap_count);
return -1;
}
return 0;
}
if (lapic_busy()) { if (lapic_busy()) {
printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
@ -671,11 +652,6 @@ static void mp_initialize_cpu(void)
void smm_initiate_relocation_parallel(void) void smm_initiate_relocation_parallel(void)
{ {
if (is_x2apic_mode()) {
x2apic_send_ipi(LAPIC_DM_SMI | LAPIC_INT_LEVELTRIG, lapicid());
return;
}
if (lapic_busy()) { if (lapic_busy()) {
printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
if (apic_wait_timeout(1000 /* 1 ms */, 50)) { if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
@ -686,10 +662,14 @@ void smm_initiate_relocation_parallel(void)
} }
lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid());
if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */))
printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); if (lapic_busy()) {
else if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) {
printk(BIOS_DEBUG, "Relocation complete.\n"); printk(BIOS_DEBUG, "SMI Relocation timed out.\n");
return;
}
}
printk(BIOS_DEBUG, "Relocation complete.\n");
} }
DECLARE_SPIN_LOCK(smm_relocation_lock); DECLARE_SPIN_LOCK(smm_relocation_lock);