mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU
This patch modified the puff fmd files to support CSE Lite SKU. * Reduce the SI_ALL size to 3MiB since ME binary size is less than 2.5MiB. * Increase the FW_MAIN_A/B size to accommodate the ME_RW update binary with CSE Lite SKU. BUG=b:154561163 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1,20 +1,20 @@
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FLASH@0xff000000 0x1000000 {
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SI_ALL@0x0 0x400000 {
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SI_ALL@0x0 0x300000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x3ff000
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SI_ME@0x1000 0x2ff000
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}
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SI_BIOS@0x400000 0xc00000 {
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RW_SECTION_A@0x0 0x368000 {
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SI_BIOS@0x300000 0xd00000 {
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RW_SECTION_A@0x0 0x3e8000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x357fc0
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RW_FWID_A@0x367fc0 0x40
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FW_MAIN_A(CBFS)@0x10000 0x3d7fc0
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RW_FWID_A@0x3e7fc0 0x40
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}
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RW_SECTION_B@0x368000 0x368000 {
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RW_SECTION_B@0x3e8000 0x3e8000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x357fc0
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RW_FWID_B@0x367fc0 0x40
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FW_MAIN_B(CBFS)@0x10000 0x3d7fc0
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RW_FWID_B@0x3e7fc0 0x40
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}
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RW_MISC@0x6D0000 0x30000 {
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RW_MISC@0x7d0000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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@ -29,8 +29,8 @@ FLASH@0xff000000 0x1000000 {
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RW_SPD_CACHE(PRESERVE)@0x2f000 0x1000
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}
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# RW_LEGACY needs to be minimum of 1MB
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RW_LEGACY(CBFS)@0x700000 0x100000
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WP_RO@0x800000 0x400000 {
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RW_LEGACY(CBFS)@0x800000 0x100000
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WP_RO@0x900000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_SECTION@0x4000 0x3fc000 {
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FMAP@0x0 0x800
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@ -1,24 +1,24 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x400000 {
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SI_ALL@0x0 0x300000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x3ff000
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SI_ME@0x1000 0x2ff000
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}
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SI_BIOS@0x400000 0x1c00000 {
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SI_BIOS@0x300000 0x1d00000 {
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# Place RW_LEGACY at the start of BIOS region such that the rest
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# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
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# SPI flash only the top 16MiB actually gets memory mapped.
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RW_LEGACY(CBFS)@0x0 0x1000000
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RW_SECTION_A@0x1000000 0x3e0000 {
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RW_SECTION_A@0x1000000 0x460000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x3cffc0
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RW_FWID_A@0x3dffc0 0x40
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FW_MAIN_A(CBFS)@0x10000 0x44ffc0
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RW_FWID_A@0x45ffc0 0x40
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}
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RW_SECTION_B@0x13e0000 0x3e0000 {
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RW_SECTION_B@0x1460000 0x460000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x3cffc0
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RW_FWID_B@0x3dffc0 0x40
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FW_MAIN_B(CBFS)@0x10000 0x44ffc0
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RW_FWID_B@0x45ffc0 0x40
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}
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RW_MISC@0x17c0000 0x40000 {
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RW_MISC@0x18c0000 0x40000 {
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UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x20000
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@ -34,7 +34,7 @@ FLASH@0xfe000000 0x2000000 {
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}
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO@0x1800000 0x400000 {
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WP_RO@0x1900000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_SECTION@0x4000 0x3fc000 {
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FMAP@0x0 0x800
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