mb, soc: change mainboard_memory_init_params prototype

The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass

Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/romstage.c

@@ -7,8 +7,9 @@
 #include <soc/romstage.h>
 #include <string.h>
 
-void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
+void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
 	const struct mb_cfg *mem_config = variant_memory_params();
 	bool half_populated = variant_is_half_populated();
 	struct mem_spd spd_info;

src/mainboard/intel/adlrvp/romstage_fsp_params.c

@@ -42,8 +42,9 @@ static void configure_external_clksrc(FSP_M_CONFIG *m_cfg)
 		m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER;
 }
 
-void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
+void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
 	const struct mb_cfg *mem_config = variant_memory_params();
 	int board_id = get_board_id();
 	const bool half_populated = false;

src/mainboard/intel/shadowmountain/romstage.c

@@ -7,8 +7,9 @@
 #include <soc/meminit.h>
 #include <baseboard/variants.h>
 
-void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
+void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
 	const struct mb_cfg *mem_config = variant_memory_params();
 	const bool half_populated = false;
 

src/mainboard/prodrive/atlas/romstage_fsp_params.c

@@ -27,8 +27,9 @@ static const struct mb_cfg ddr5_mem_config = {
 	}
 };
 
-void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
+void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
 	const struct mb_cfg *mem_config = &ddr5_mem_config;
 	const bool half_populated = false;
 

src/soc/intel/alderlake/include/soc/romstage.h

@@ -6,7 +6,7 @@
 #include <fsp/api.h>
 #include <stddef.h>
 
-void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg);
+void mainboard_memory_init_params(FSPM_UPD *memupd);
 void systemagent_early_init(void);
 
 /* Board type */

src/soc/intel/alderlake/romstage/fsp_params.c

@@ -361,10 +361,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	config = config_of_soc();
 
 	soc_memory_init_params(m_cfg, config);
-	mainboard_memory_init_params(m_cfg);
+	mainboard_memory_init_params(mupd);
 }
 
-__weak void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
+__weak void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }