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mb/google/fizz: update DPTF settings 

TCPU:
  _CRT: 100
  _PSV: 93
  _TRT: 100/5(s)
TSR0:
  _CRT: 83
  _PSV: 70
  _TRT: 100/10(s)
TSR1:
  _CRT: 73
  _PSV: 67
  _TRT: 100/30(s)

TCC: 6 for 94'C

PL1:
  max: 15W
  min: 3W

BUG=b:70294260
BRANCH=master
TEST=build
Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kevin Chiu 2018-01-08 11:50:59 +08:00 committed by Martin Roth
parent e13a269f58
commit 09f8a834b3
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/fizz/acpi/dptf.asl
View File

@ -14,15 +14,15 @@
* GNU General Public License for more details.
*/
#define DPTF_CPU_PASSIVE 85
#define DPTF_CPU_CRITICAL 99
#define DPTF_CPU_PASSIVE 93
#define DPTF_CPU_CRITICAL 100
#define DPTF_CPU_ACTIVE_AC0 90
#define DPTF_CPU_ACTIVE_AC1 77
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
#define DPTF_TSR0_PASSIVE 66
#define DPTF_TSR0_CRITICAL 71
#define DPTF_TSR0_PASSIVE 70
#define DPTF_TSR0_CRITICAL 83
#define DPTF_TSR0_ACTIVE_AC0 95
#define DPTF_TSR0_ACTIVE_AC1 85
#define DPTF_TSR0_ACTIVE_AC2 60
@ -33,18 +33,18 @@
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom"
#define DPTF_TSR1_PASSIVE 65
#define DPTF_TSR1_CRITICAL 70
#define DPTF_TSR1_PASSIVE 67
#define DPTF_TSR1_CRITICAL 73
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 0 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 1 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
@ -52,7 +52,7 @@ Name (MPPC, Package ()
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
1600, /* PowerLimitMinimum */
3000, /* PowerLimitMinimum */
15000, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */

2
src/mainboard/google/fizz/devicetree.cb
View File

@ -267,7 +267,7 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
register "tdp_psyspl2" = "90"
register "tcc_offset" = "10" # TCC of 90C
register "tcc_offset" = "6" # TCC of 94C
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_A7"