sdm845: Add GPIO API
Introduces new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I8cef9dae2072da32cb0678efefeb8f0070cdde9c Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/26233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
David Dai
Julius Werner
parent
3044af7adc
commit
09fbaaaff7
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@ -6,21 +6,25 @@ bootblock-y += bootblock.c
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bootblock-y += spi.c
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bootblock-y += mmu.c
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bootblock-y += timer.c
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bootblock-y += gpio.c
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################################################################################
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verstage-y += spi.c
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verstage-y += timer.c
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verstage-y += gpio.c
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################################################################################
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romstage-y += spi.c
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romstage-y += cbmem.c
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romstage-y += timer.c
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romstage-y += gpio.c
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################################################################################
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ramstage-y += soc.c
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ramstage-y += spi.c
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ramstage-y += cbmem.c
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ramstage-y += timer.c
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ramstage-y += gpio.c
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################################################################################
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@ -0,0 +1,76 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Qualcomm Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <types.h>
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#include <console/console.h>
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#include <delay.h>
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#include <timer.h>
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#include <timestamp.h>
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#include <gpio.h>
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void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
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uint32_t drive_str, uint32_t enable)
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{
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uint32_t reg_val;
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) |
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((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) |
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((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) |
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((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT);
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write32(®s->cfg, reg_val);
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}
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void gpio_set(gpio_t gpio, int value)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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write32(®s->in_out, (!!value) << GPIO_IO_OUT_SHFT);
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}
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int gpio_get(gpio_t gpio)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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return ((read32(®s->in_out) >> GPIO_IO_IN_SHFT) &
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GPIO_IO_IN_BMSK);
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}
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void gpio_input_pulldown(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_DISABLE,
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GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE);
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}
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void gpio_input_pullup(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_DISABLE,
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GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE);
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}
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void gpio_input(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_DISABLE,
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GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE);
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}
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void gpio_output(gpio_t gpio, int value)
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{
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gpio_set(gpio, value);
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gpio_configure(gpio, GPIO_FUNC_DISABLE,
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GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE);
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2018 Qualcomm Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
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#define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
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#include <stdint.h>
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#define QSPI_BASE 0x88DF000
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#define TLMM_EAST_TILE_BASE 0x03500000
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#define TLMM_NORTH_TILE_BASE 0x03900000
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#define TLMM_SOUTH_TILE_BASE 0x03D00000
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#endif /* __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ */
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@ -17,7 +17,336 @@
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#define _SOC_QUALCOMM_SDM845_GPIO_H_
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#include <types.h>
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#include <soc/addressmap.h>
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typedef u32 gpio_t;
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typedef struct {
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u32 addr;
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} gpio_t;
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#define TLMM_TILE_SIZE 0x00400000
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#define TLMM_GPIO_OFF_DELTA 0x00001000
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#define TLMM_GPIO_TILE_NUM 3
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#define TLMM_GPIO_IN_OUT_OFF 0x4
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#define TLMM_GPIO_ID_STATUS_OFF 0x10
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#define GPIO_FUNC_ENABLE 1
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#define GPIO_FUNC_DISABLE 0
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/* GPIO TLMM: Direction */
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#define GPIO_INPUT 0
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#define GPIO_OUTPUT 1
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/* GPIO TLMM: Pullup/Pulldown */
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#define GPIO_NO_PULL 0
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#define GPIO_PULL_DOWN 1
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#define GPIO_KEEPER 2
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#define GPIO_PULL_UP 3
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/* GPIO TLMM: Drive Strength */
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#define GPIO_2MA 0
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#define GPIO_4MA 1
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#define GPIO_6MA 2
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#define GPIO_8MA 3
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#define GPIO_10MA 4
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#define GPIO_12MA 5
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#define GPIO_14MA 6
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#define GPIO_16MA 7
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/* GPIO TLMM: Status */
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#define GPIO_DISABLE 0
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#define GPIO_ENABLE 1
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/* GPIO TLMM: Mask */
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#define GPIO_CFG_PULL_BMSK 0x3
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#define GPIO_CFG_FUNC_BMSK 0xF
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#define GPIO_CFG_DRV_BMSK 0x7
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#define GPIO_CFG_OE_BMSK 0x1
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/* GPIO TLMM: Shift */
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#define GPIO_CFG_PULL_SHFT 0
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#define GPIO_CFG_FUNC_SHFT 2
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#define GPIO_CFG_DRV_SHFT 6
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#define GPIO_CFG_OE_SHFT 9
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/* GPIO IO: Mask */
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#define GPIO_IO_IN_BMSK 0x1
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#define GPIO_IO_OUT_BMSK 0x1
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/* GPIO IO: Shift */
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#define GPIO_IO_IN_SHFT 0
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#define GPIO_IO_OUT_SHFT 1
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/* GPIO ID STATUS: Mask */
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#define GPIO_ID_STATUS_BMSK 0x1
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/* GPIO MAX Valid # */
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#define GPIO_NUM_MAX 149
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#define GPIO_FUNC_GPIO 0
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#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR})
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#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \
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GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \
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GPIO##index##_FUNC_##func1 = 1, \
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GPIO##index##_FUNC_##func2 = 2, \
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GPIO##index##_FUNC_##func3 = 3, \
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GPIO##index##_FUNC_##func4 = 4, \
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GPIO##index##_FUNC_##func5 = 5, \
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GPIO##index##_FUNC_##func6 = 6, \
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GPIO##index##_FUNC_##func7 = 7
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enum {
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PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5,
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RES_6, RES_7),
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PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(17, SOUTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3,
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RES_4, RES_5, RES_6, RES_7),
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PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,
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RES_6, RES_7),
|
||||
PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0,
|
||||
MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT),
|
||||
PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB,
|
||||
RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3,
|
||||
RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3,
|
||||
RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
};
|
||||
|
||||
struct tlmm_gpio {
|
||||
uint32_t cfg;
|
||||
uint32_t in_out;
|
||||
};
|
||||
|
||||
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
|
||||
uint32_t drive_str, uint32_t enable);
|
||||
|
||||
#endif // _SOC_QUALCOMM_SDM845_GPIO_H_
|
||||
|
|
|
|||
Loading…
Reference in New Issue