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sb/amd/sb700: Enable watchdog timer for OS use 

Change-Id: Ib0281139cafe74a22a24a377b3fdec1c59e934f3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12687
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-12-08 12:09:06 -06:00 committed by Martin Roth
parent e7cd0f889e
commit 0a105cd067
2 changed files with 21 additions and 1 deletions
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3
src/southbridge/amd/sb700/early_setup.c
View File

@ -684,7 +684,8 @@ static void sb700_pci_cfg(void)
/* SMBus Device, BDF:0-20-0 */ /* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
/* Enable watchdog decode timer */
/* Enable watchdog timer decode */
byte = pci_read_config8(dev, 0x41); byte = pci_read_config8(dev, 0x41);
byte |= (1 << 3); byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte); pci_write_config8(dev, 0x41, byte);

19
src/southbridge/amd/sb700/sm.c
View File

@ -30,6 +30,9 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define SB_MMIO_CFG_REG 0x9c
#define SB_MMIO_BASE_ADDRESS 0xfeb00000
#define PRIMARY_SMBUS_RESOURCE_NUMBER 0x90 #define PRIMARY_SMBUS_RESOURCE_NUMBER 0x90
#define AUXILIARY_SMBUS_RESOURCE_NUMBER 0x58 #define AUXILIARY_SMBUS_RESOURCE_NUMBER 0x58
@ -283,6 +286,13 @@ static void sm_init(device_t dev)
byte |= 1 << 3; byte |= 1 << 3;
pci_write_config8(dev, 0x43, byte); pci_write_config8(dev, 0x43, byte);
/* Enable southbridge MMIO decode */
dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
dword &= ~(0xffffff << 8);
dword |= SB_MMIO_BASE_ADDRESS;
dword |= 0x1;
pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
} }
//ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER //ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER
byte = pci_read_config8(dev, 0xAE); byte = pci_read_config8(dev, 0xAE);
@ -417,6 +427,15 @@ static void sb700_sm_read_resources(device_t dev)
res->gran = 8; res->gran = 8;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* SB MMIO / WDT */
res = new_resource(dev, SB_MMIO_CFG_REG);
res->base = SB_MMIO_BASE_ADDRESS;
res->size = 0x1000;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* HPET */ /* HPET */
res = new_resource(dev, 0xB4); /* TODO: test hpet */ res = new_resource(dev, 0xB4); /* TODO: test hpet */
res->base = 0xfed00000; /* reset hpet to widely accepted address */ res->base = 0xfed00000; /* reset hpet to widely accepted address */