google/kahlee: Add mainboard GPIOs to ACPI
Add the Google mainboard GPIOs to the ACPI table. Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -18,7 +18,10 @@
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <boot/coreboot_tables.h>
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#include <console/console.h>
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#include <soc/gpio.h>
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/* SPI Write protect */
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#define CROS_WP_GPIO GPIO_122
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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@ -33,5 +36,15 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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int get_write_protect_state(void)
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{
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return 0;
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return gpio_get(CROS_WP_GPIO);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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@ -19,6 +19,7 @@
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#include <agesawrapper.h>
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#include <amd_pci_util.h>
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#include <ec.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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@ -91,6 +92,8 @@ static void kahlee_enable(device_t dev)
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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}
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struct chip_operations mainboard_ops = {
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