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soc/intel/alderlake: Add config option for S3 ACPI 

Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust
the ACPI to not offer D3Cold when using S3.

This patch is the Alder Lake equivalent of CB:59024.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Sean Rhodes 2022-05-21 10:38:09 +01:00 committed by Felix Held
parent 843f34e32a
commit 0a16291919
5 changed files with 61 additions and 1 deletions
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6
src/soc/intel/alderlake/Kconfig
View File

@ -292,6 +292,12 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 8
config SOC_INTEL_ALDERLAKE_S3
bool
default n
help
Select if using S3 instead of S0ix to disable D3Cold.
config SOC_INTEL_UART_DEV_MAX
int
default 7

8
src/soc/intel/alderlake/acpi/tcss.asl
View File

@ -41,6 +41,12 @@
Scope (\_SB)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Name (S0IX, 0)
#else
Name (S0IX, 1)
#endif
/* Device base address */
Method (BASE, 1)
{
@ -573,6 +579,7 @@ Scope (\_SB.PCI0)
}
}
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@ -643,6 +650,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
#endif
/*
* TCSS xHCI device

22
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@ -28,25 +28,45 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
Return (0x4)
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Return (0x04)
#else
Return (0x03)
#endif
}
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If (DUID == 0) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
}
/*

20
src/soc/intel/alderlake/acpi/tcss_pcierp.asl
View File

@ -267,25 +267,45 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Return (0x4)
#else
Return (0x3)
#endif
}
Method (_PR0)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
}
Method (_PR3)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
#else
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
#endif
}
/*

6
src/soc/intel/alderlake/acpi/tcss_xhci.asl
View File

@ -30,7 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Return (0x4)
#else
Return (0x3)
#endif
}
/*
@ -39,6 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@ -48,6 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
#endif
/*
* XHCI controller _DSM method