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nb,soc/intel: Handle upper RAM boundary 

Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2021-06-28 21:43:31 +03:00 committed by Felix Held
parent e0ddbbb0d2
commit 0a18d64d00
12 changed files with 25 additions and 68 deletions
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26
src/northbridge/intel/e7505/northbridge.c
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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/device.h> #include <device/device.h>
@ -11,9 +12,8 @@
static void mch_domain_read_resources(struct device *dev) static void mch_domain_read_resources(struct device *dev)
{ {
int idx; int idx;
unsigned long tomk, tolmk; unsigned long tolmk;
unsigned long remapbasek, remaplimitk; uint64_t tom, remapbase, remaplimit;
const unsigned long basek_4G = 4 * (GiB / KiB);
struct device *mc_dev; struct device *mc_dev;
pci_domain_read_resources(dev); pci_domain_read_resources(dev);
@ -25,28 +25,26 @@ static void mch_domain_read_resources(struct device *dev)
tolmk = pci_read_config16(mc_dev, TOLM) >> 11; tolmk = pci_read_config16(mc_dev, TOLM) >> 11;
tolmk <<= 17; tolmk <<= 17;
tomk = pci_read_config8(mc_dev, DRB_ROW_7); tom = pci_read_config8(mc_dev, DRB_ROW_7);
tomk <<= 16; tom <<= 26;
/* Remapped region with a 64 MiB granularity in register /* Remapped region with a 64 MiB granularity in register
definition. Limit is inclusive, so add one. */ definition. Limit is inclusive, so add one. */
remapbasek = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff; remapbase = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff;
remapbasek <<= 16; remapbase <<= 26;
remaplimitk = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff; remaplimit = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff;
remaplimitk += 1; remaplimit += 1;
remaplimitk <<= 16; remaplimit <<= 26;
/* Report the memory regions */ /* Report the memory regions */
idx = 10; idx = 10;
ram_resource_kb(dev, idx++, 0, tolmk); ram_resource_kb(dev, idx++, 0, tolmk);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
if (tomk > basek_4G)
ram_resource_kb(dev, idx++, basek_4G, tomk - basek_4G);
if (remaplimitk > remapbasek) ASSERT(tom == remapbase);
ram_resource_kb(dev, idx++, remapbasek, remaplimitk - remapbasek); upper_ram_end(dev, idx++, remaplimit);
} }
static void mch_domain_set_resources(struct device *dev) static void mch_domain_set_resources(struct device *dev)

7
src/northbridge/intel/gm45/northbridge.c
View File

@ -121,12 +121,7 @@ static void mch_domain_read_resources(struct device *dev)
* If >= 4GB installed then memory from TOLUD to 4GB * If >= 4GB installed then memory from TOLUD to 4GB
* is remapped above TOM, TOUUD will account for both * is remapped above TOM, TOUUD will account for both
*/ */
touud >>= 10; /* Convert to KB */ upper_ram_end(dev, idx++, touud);
if (touud > 4096 * 1024) {
ram_resource_kb(dev, idx++, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud >> 10) - 4096);
}
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
"size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);

8
src/northbridge/intel/haswell/northbridge.c
View File

@ -237,7 +237,7 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values)
static void mc_add_dram_resources(struct device *dev, int *resource_cnt) static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
{ {
unsigned long base_k, size_k, touud_k, index; unsigned long base_k, size_k, index;
struct resource *resource; struct resource *resource;
uint64_t mc_values[NUM_MAP_ENTRIES]; uint64_t mc_values[NUM_MAP_ENTRIES];
@ -312,11 +312,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
} }
/* 4GiB -> TOUUD */ /* 4GiB -> TOUUD */
base_k = 4096 * 1024; /* 4GiB */ upper_ram_end(dev, index++, mc_values[TOUUD_REG]);
touud_k = mc_values[TOUUD_REG] >> 10;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource_kb(dev, index++, base_k, size_k);
/* Reserve everything between A segment and 1MB: /* Reserve everything between A segment and 1MB:
* *

3
src/northbridge/intel/ironlake/northbridge.c
View File

@ -134,8 +134,7 @@ static void mc_read_resources(struct device *dev)
mmio_resource_kb(dev, index++, gtt_base / KiB, uma_size_gtt * KiB); mmio_resource_kb(dev, index++, gtt_base / KiB, uma_size_gtt * KiB);
mmio_resource_kb(dev, index++, igd_base / KiB, uma_size_igd * KiB); mmio_resource_kb(dev, index++, igd_base / KiB, uma_size_igd * KiB);
if (touud > 4096) upper_ram_end(dev, index++, touud * MiB);
ram_resource_kb(dev, index++, (4096 * KiB), ((touud - 4096) * KiB));
/* This memory is not DMA-capable. */ /* This memory is not DMA-capable. */
if (touud >= 8192 - 64) if (touud >= 8192 - 64)

8
src/northbridge/intel/pineview/northbridge.c
View File

@ -44,7 +44,6 @@ static void mch_domain_read_resources(struct device *dev)
u32 tomk, tolud, tseg_sizek; u32 tomk, tolud, tseg_sizek;
u32 cbmem_topk, delta_cbmem; u32 cbmem_topk, delta_cbmem;
u16 index; u16 index;
const u32 top32memk = 4 * (GiB / KiB);
struct device *mch = pcidev_on_root(0, 0); struct device *mch = pcidev_on_root(0, 0);
@ -108,12 +107,7 @@ static void mch_domain_read_resources(struct device *dev)
* If > 4GB installed then memory from TOLUD to 4GB * If > 4GB installed then memory from TOLUD to 4GB
* is remapped above TOM, TOUUD will account for both * is remapped above TOM, TOUUD will account for both
*/ */
touud >>= 10; /* Convert to KB */ upper_ram_end(dev, index++, touud);
if (touud > top32memk) {
ram_resource_kb(dev, index++, top32memk, touud - top32memk);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud - top32memk) / KiB);
}
mmconf_resource(dev, index++); mmconf_resource(dev, index++);

6
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -211,11 +211,7 @@ static void mc_read_resources(struct device *dev)
* If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM. * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM.
* TOUUD will account for both memory chunks. * TOUUD will account for both memory chunks.
*/ */
touud >>= 10; /* Convert to KB */ upper_ram_end(dev, index++, touud);
if (touud > 4096 * 1024) {
ram_resource_kb(dev, index++, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096);
}
add_fixed_resources(dev, index++); add_fixed_resources(dev, index++);
} }

7
src/northbridge/intel/x4x/northbridge.c
View File

@ -88,12 +88,7 @@ static void mch_domain_read_resources(struct device *dev)
* If >= 4GB installed then memory from TOLUD to 4GB * If >= 4GB installed then memory from TOLUD to 4GB
* is remapped above TOM, TOUUD will account for both * is remapped above TOM, TOUUD will account for both
*/ */
touud >>= 10; /* Convert to KB */ upper_ram_end(dev, index++, touud);
if (touud > top32memk) {
ram_resource_kb(dev, index++, top32memk, touud - top32memk);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud - top32memk) >> 10);
}
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n", printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n",
tomk << 10, uma_sizek << 10); tomk << 10, uma_sizek << 10);

3
src/soc/intel/baytrail/northcluster.c
View File

@ -100,8 +100,7 @@ static void nc_read_resources(struct device *dev)
*/ */
bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
bmbound_hi <<= 4; bmbound_hi <<= 4;
if (bmbound_hi > 4ull * GiB) upper_ram_end(dev, index++, bmbound_hi);
ram_from_to(dev, index++, 4ull * GiB, bmbound_hi);
/* /*
* Reserve everything between A segment and 1MB: * Reserve everything between A segment and 1MB:

3
src/soc/intel/braswell/northcluster.c
View File

@ -116,8 +116,7 @@ static void nc_read_resources(struct device *dev)
*/ */
bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
bmbound_hi <<= 4; bmbound_hi <<= 4;
if (bmbound_hi > 4ull * GiB) upper_ram_end(dev, index++, bmbound_hi);
ram_from_to(dev, index++, 4ull * GiB, bmbound_hi);
/* /*
* Reserve everything between A segment and 1MB: * Reserve everything between A segment and 1MB:

7
src/soc/intel/broadwell/northbridge.c
View File

@ -259,7 +259,6 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values)
static void mc_add_dram_resources(struct device *dev, int *resource_cnt) static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
{ {
unsigned long base_k, size_k; unsigned long base_k, size_k;
unsigned long touud_k;
unsigned long index; unsigned long index;
struct resource *resource; struct resource *resource;
uint64_t mc_values[NUM_MAP_ENTRIES]; uint64_t mc_values[NUM_MAP_ENTRIES];
@ -342,11 +341,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
IORESOURCE_ASSIGNED; IORESOURCE_ASSIGNED;
/* 4GiB -> TOUUD */ /* 4GiB -> TOUUD */
base_k = 4096 * 1024; /* 4GiB */ upper_ram_end(dev, index++, mc_values[TOUUD_REG]);
touud_k = mc_values[TOUUD_REG] >> 10;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource_kb(dev, index++, base_k, size_k);
/* Reserve everything between A segment and 1MB: /* Reserve everything between A segment and 1MB:
* *

8
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -186,7 +186,7 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
*/ */
static void sa_add_dram_resources(struct device *dev, int *resource_count) static void sa_add_dram_resources(struct device *dev, int *resource_count)
{ {
uintptr_t base_k, touud_k; uintptr_t base_k;
size_t size_k; size_t size_k;
uint64_t sa_map_values[MAX_MAP_ENTRIES]; uint64_t sa_map_values[MAX_MAP_ENTRIES];
uintptr_t top_of_ram; uintptr_t top_of_ram;
@ -212,11 +212,7 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
mmio_resource_kb(dev, index++, base_k / KiB, size_k / KiB); mmio_resource_kb(dev, index++, base_k / KiB, size_k / KiB);
/* 4GiB -> TOUUD */ /* 4GiB -> TOUUD */
base_k = 4 * (GiB / KiB); /* 4GiB */ upper_ram_end(dev, index++, sa_map_values[SA_TOUUD_REG]);
touud_k = sa_map_values[SA_TOUUD_REG] / KiB;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource_kb(dev, index++, base_k, size_k);
/* /*
* Reserve everything between A segment and 1MB: * Reserve everything between A segment and 1MB:

7
src/soc/intel/denverton_ns/systemagent.c
View File

@ -191,7 +191,6 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values)
static void mc_add_dram_resources(struct device *dev) static void mc_add_dram_resources(struct device *dev)
{ {
unsigned long base_k, size_k; unsigned long base_k, size_k;
unsigned long touud_k;
unsigned long index; unsigned long index;
struct resource *resource; struct resource *resource;
uint64_t mc_values[NUM_MAP_ENTRIES]; uint64_t mc_values[NUM_MAP_ENTRIES];
@ -262,11 +261,7 @@ static void mc_add_dram_resources(struct device *dev)
IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
/* 4GiB -> TOUUD */ /* 4GiB -> TOUUD */
base_k = 4096 * 1024; /* 4GiB */ upper_ram_end(dev, index++, mc_values[TOUUD_REG]);
touud_k = mc_values[TOUUD_REG] >> 10;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource_kb(dev, index++, base_k, size_k);
/* /*
* Reserve everything between A segment and 1MB: * Reserve everything between A segment and 1MB: