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lenovo/x200: Revise onboard IRQ routing 

All southbridge interrupt pin and routing registers (D*IP and D*IR)
are left at their default values (see ICH9 datasheet) and this file
just has to reflect them.

Change-Id: I687262556d918311757fda9afda9ebfdd7edf947
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12813
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Nico Huber 2015-12-29 23:35:37 +01:00 committed by Martin Roth
parent 08debacad1
commit 0a207399ce
1 changed files with 12 additions and 12 deletions
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24
src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl
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@ -28,6 +28,8 @@ Method(_PRT)
Package() { 0x0001ffff, 0, 0, 16 }, Package() { 0x0001ffff, 0, 0, 16 },
// Onboard graphics (IGD) 0:2.0 // Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 }, Package() { 0x0002ffff, 0, 0, 16 },
// Onboard GbE
Package() { 0x0019ffff, 0, 0, 16 },
// USB and EHCI 0:1a.x // USB and EHCI 0:1a.x
Package() { 0x001affff, 0, 0, 16 }, Package() { 0x001affff, 0, 0, 16 },
Package() { 0x001affff, 1, 0, 17 }, Package() { 0x001affff, 1, 0, 17 },
@ -36,16 +38,14 @@ Method(_PRT)
Package() { 0x001bffff, 0, 0, 16 }, Package() { 0x001bffff, 0, 0, 16 },
// PCIe Root Ports 0:1c.x // PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 16 }, Package() { 0x001cffff, 0, 0, 16 },
Package() { 0x001cffff, 1, 0, 17 },
Package() { 0x001cffff, 2, 0, 18 },
Package() { 0x001cffff, 3, 0, 19 },
// USB and EHCI 0:1d.x // USB and EHCI 0:1d.x
Package() { 0x001dffff, 0, 0, 16 }, Package() { 0x001dffff, 0, 0, 16 },
Package() { 0x001dffff, 1, 0, 17 }, Package() { 0x001dffff, 1, 0, 17 },
Package() { 0x001dffff, 2, 0, 18 }, Package() { 0x001dffff, 2, 0, 18 },
// FIXME // LPC bridge sub devices 0:1f.x
// CardBus/IEEE1394 0:1e.2, 0:1e.3
// Package() { 0x001effff, 0, 0, 22 },
// Package() { 0x001effff, 1, 0, 20 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, 0, 16 },
Package() { 0x001fffff, 1, 0, 17 }, Package() { 0x001fffff, 1, 0, 17 },
Package() { 0x001fffff, 2, 0, 18 } Package() { 0x001fffff, 2, 0, 18 }
}) })
@ -55,6 +55,8 @@ Method(_PRT)
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// Onboard graphics (IGD) 0:2.0 // Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// Onboard GbE
Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// USB and EHCI 0:1a.x // USB and EHCI 0:1a.x
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
@ -63,16 +65,14 @@ Method(_PRT)
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x // PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
// USB and EHCI 0:1d.x // USB and EHCI 0:1d.x
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
// FIXME // LPC bridge sub devices 0:1f.x
// CardBus/IEEE1394 0:1e.2, 0:1e.3
// Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
// Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }
}) })