lib/stage_cache: Refactor Kconfig options
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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src/Kconfig
26
src/Kconfig
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@ -250,12 +250,28 @@ config RELOCATABLE_RAMSTAGE
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wake. When selecting this option the romstage is responsible for
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determing a stack location to use for loading the ramstage.
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config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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depends on RELOCATABLE_RAMSTAGE
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config TSEG_STAGE_CACHE
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bool
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default y
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depends on !NO_STAGE_CACHE && SMM_TSEG
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help
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The relocated ramstage is saved in an area specified by the
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by the board and/or chipset.
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The option enables stage cache support for platform. Platform
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can stash copies of postcar, ramstage and raw runtime data
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inside SMM TSEG, to be restored on S3 resume path.
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config CBMEM_STAGE_CACHE
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bool "Cache stages in CBMEM"
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depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE
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help
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The option enables stage cache support for platform. Platform
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can stash copies of postcar, ramstage and raw runtime data
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inside CBMEM.
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While the approach is faster than reloading stages from boot media
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it is also a possible attack scenario via which OS can possibly
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circumvent SMM locks and SPI write protections.
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If unsure, select 'N'
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config UPDATE_IMAGE
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bool "Update existing coreboot.rom image"
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@ -1143,7 +1159,7 @@ config RELOCATABLE_MODULES
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config NO_STAGE_CACHE
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bool
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default y if !HAVE_ACPI_RESUME
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default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
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help
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Do not save any component in stage cache for resume path. On resume,
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all components would be read back from CBFS again.
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@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS
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select CPU_INTEL_COMMON
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select NO_FIXED_XIP_ROM_SIZE
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select PARALLEL_MP
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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config BOOTBLOCK_CPU_INIT
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string
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@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
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#select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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select CPU_INTEL_COMMON
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select PARALLEL_MP
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select NO_FIXED_XIP_ROM_SIZE
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@ -121,7 +121,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
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}
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/* Adjust available SMM handler memory size. */
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if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
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if (CONFIG(TSEG_STAGE_CACHE)) {
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ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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}
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@ -32,8 +32,7 @@ enum {
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STAGE_S3_DATA,
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};
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#if CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) \
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|| CONFIG(RELOCATABLE_RAMSTAGE)
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#if CONFIG(TSEG_STAGE_CACHE) || CONFIG(CBMEM_STAGE_CACHE)
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/* Cache the loaded stage provided according to the parameters. */
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void stage_cache_add(int stage_id, const struct prog *stage);
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/* Load the cached stage at given location returning the stage entry point. */
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@ -176,16 +176,13 @@ verstage-$(CONFIG_REG_SCRIPT) += reg_script.c
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romstage-$(CONFIG_REG_SCRIPT) += reg_script.c
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ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
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ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y)
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ramstage-y += ext_stage_cache.c
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romstage-y += ext_stage_cache.c
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postcar-y += ext_stage_cache.c
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else
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ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
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romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
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postcar-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
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endif
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ramstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c
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romstage-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c
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postcar-$(CONFIG_TSEG_STAGE_CACHE) += ext_stage_cache.c
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ramstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c
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romstage-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c
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postcar-$(CONFIG_CBMEM_STAGE_CACHE) += cbmem_stage_cache.c
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romstage-y += boot_device.c
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ramstage-y += boot_device.c
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@ -29,7 +29,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select PARALLEL_MP
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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config CBFS_SIZE
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hex
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@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL
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select CACHE_MRC_SETTINGS
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select INTEL_DDI
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select INTEL_GMA_ACPI
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select C_ENVIRONMENT_BOOTBLOCK
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@ -30,7 +30,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select PARALLEL_MP
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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def_bool n
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@ -31,7 +31,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select PARALLEL_MP
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select C_ENVIRONMENT_BOOTBLOCK
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config BOOTBLOCK_NORTHBRIDGE_INIT
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@ -29,7 +29,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select PARALLEL_MP
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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config CBFS_SIZE
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hex
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@ -52,7 +52,6 @@ config CPU_SPECIFIC_OPTIONS
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select C_ENVIRONMENT_BOOTBLOCK
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select HAVE_SMI_HANDLER
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@ -73,7 +73,6 @@ config CPU_SPECIFIC_OPTIONS
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select C_ENVIRONMENT_BOOTBLOCK
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select HAVE_SMI_HANDLER
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@ -40,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS
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# Misc options
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select C_ENVIRONMENT_BOOTBLOCK
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COLLECT_TIMESTAMPS
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select COMMON_FADT
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select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
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@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_VERSTAGE_X86_32
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COLLECT_TIMESTAMPS
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select SUPPORT_CPU_UCODE_IN_CBFS
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select MICROCODE_BLOB_NOT_IN_BLOB_REPO
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@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select MRC_SETTINGS_PROTECT
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_SMI_HANDLER
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@ -59,7 +59,6 @@ config CPU_SPECIFIC_OPTIONS
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select BOOT_DEVICE_SUPPORTS_WRITES
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select C_ENVIRONMENT_BOOTBLOCK
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COMMON_FADT
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select CPU_INTEL_COMMON
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS
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select BOOT_DEVICE_SUPPORTS_WRITES
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select C_ENVIRONMENT_BOOTBLOCK
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COMMON_FADT
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select FSP_M_XIP
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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select COLLECT_TIMESTAMPS
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select COMMON_FADT
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select CPU_INTEL_COMMON
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