soc/amd: introduce and use PSTATE_MSR macro

Instead of adding the P-state number to the PSTATE_0_MSR number to get
the P-state MSR number for the rdmsr call, provide a macro that directly
calculates the MSR number for a given power state. Also drop the unused
PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs
available in the hardware.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/include/cpu/amd/msr.h

@@ -40,10 +40,7 @@
 	/* P-state Status Register */
 #define PS_STS_REG			0xC0010063
 #define PSTATE_0_MSR			0xC0010064
-#define PSTATE_1_MSR			0xC0010065
-#define PSTATE_2_MSR			0xC0010066
-#define PSTATE_3_MSR			0xC0010067
-#define PSTATE_4_MSR			0xC0010068
+#define PSTATE_MSR(pstate)		(PSTATE_0_MSR + (pstate))
 #define MSR_PATCH_LOADER		0xC0010020
 
 #define MSR_COFVID_STS			0xC0010071

src/soc/amd/cezanne/acpi.c

@@ -200,7 +200,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
 
 	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_0_MSR + pstate);
+		pstate_def = rdmsr(PSTATE_MSR(pstate));
 
 		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
 				>> PSTATE_DEF_HI_ENABLE_SHIFT;

src/soc/amd/common/block/cpu/tsc/tsc_freq.c

@@ -22,7 +22,7 @@ unsigned long tsc_freq_mhz(void)
 		return mhz;
 
 	high_state = rdmsr(PS_LIM_REG).lo & 0x7;
-	msr = rdmsr(PSTATE_0_MSR + high_state);
+	msr = rdmsr(PSTATE_MSR(high_state));
 	if (!(msr.hi & 0x80000000))
 		die("Unknown error: cannot determine P-state 0\n");
 

src/soc/amd/glinda/acpi.c

@@ -203,7 +203,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
 
 	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_0_MSR + pstate);
+		pstate_def = rdmsr(PSTATE_MSR(pstate));
 
 		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
 				>> PSTATE_DEF_HI_ENABLE_SHIFT;

src/soc/amd/mendocino/acpi.c

@@ -202,7 +202,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
 
 	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_0_MSR + pstate);
+		pstate_def = rdmsr(PSTATE_MSR(pstate));
 
 		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
 				>> PSTATE_DEF_HI_ENABLE_SHIFT;

src/soc/amd/phoenix/acpi.c

@@ -203,7 +203,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
 
 	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_0_MSR + pstate);
+		pstate_def = rdmsr(PSTATE_MSR(pstate));
 
 		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
 				>> PSTATE_DEF_HI_ENABLE_SHIFT;

src/soc/amd/picasso/acpi.c

@@ -202,7 +202,7 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 	max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
 
 	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_def = rdmsr(PSTATE_0_MSR + pstate);
+		pstate_def = rdmsr(PSTATE_MSR(pstate));
 
 		pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
 				>> PSTATE_DEF_HI_ENABLE_SHIFT;

src/soc/amd/stoneyridge/tsc_freq.c

@@ -23,7 +23,7 @@ unsigned long tsc_freq_mhz(void)
 	boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
 			>> 2) & 0x7;
 
-	msr = rdmsr(PSTATE_0_MSR + boost_states);
+	msr = rdmsr(PSTATE_MSR(boost_states));
 	if (!(msr.hi & 0x80000000))
 		die("Unknown error: cannot determine P-state 0\n");