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soc/amd/common: Add GPIO config for native func w/ output drive 

Our existing native function gpio configuration macro (PAD_NF) only sets
the pull.  For PCIe reset, we now need to be able to set it to its
native function (PCIE_RST_L), and drive it low, then high.

BUG=b:182805349
TEST=Configure GPIO, see correct behavior.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I636371517c99f94f76834abc4575795d51aa0368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2021-06-15 11:19:57 -06:00 committed by Martin Roth
parent 1687c243f5
commit 0a5837e9f1
1 changed files with 5 additions and 1 deletions
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6
src/soc/amd/common/block/include/amdblocks/gpio_defs.h
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@ -208,10 +208,14 @@
#define PAD_WAKE_ENABLE(__wake) GPIO_WAKE_ ## __wake
#define PAD_DEBOUNCE_CONFIG(__deb) GPIO_DEB_ ## __deb
/* Native function pad configuration */
/* Native function pad configuration with PAD_PULL */
#define PAD_NF(pin, func, pull) \
PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_PULL(pull))
/* Native function pad configuration with PAD_OUTPUT */
#define PAD_NFO(pin, func, direction) \
PAD_CFG_STRUCT(pin, pin ## _IOMUX_ ## func, PAD_OUTPUT(direction))
/* General purpose input pad configuration */
#define PAD_GPI(pin, pull) \
PAD_CFG_STRUCT(pin, pin ## _IOMUX_GPIOxx, PAD_PULL(pull))