From 0a656f033bbfb2c518b3a351d659d1585985c5b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 13 Jan 2019 18:22:08 +0200 Subject: [PATCH] Drop leftover debug function declarations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib93b816e7ab3146f6f70ad4089327cd6b7bc7c24 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30893 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: David Guckian Reviewed-by: Vanny E Reviewed-by: Nico Huber --- src/northbridge/intel/fsp_rangeley/northbridge.h | 7 ------- src/northbridge/intel/haswell/haswell.h | 5 ----- src/northbridge/intel/nehalem/nehalem.h | 6 ------ src/northbridge/intel/sandybridge/sandybridge.h | 6 ------ src/soc/intel/denverton_ns/include/soc/bootblock.h | 8 -------- src/soc/intel/fsp_baytrail/include/soc/baytrail.h | 5 ----- 6 files changed, 37 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index e3846831f8..160d75477a 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -63,13 +63,6 @@ void rangeley_late_initialization(void); u32 sideband_read(int port, int reg); void sideband_write(int port, int reg, long data); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void report_platform_info(void); - #ifndef __SIMPLE_DEVICE__ void northbridge_acpi_fill_ssdt_generator(struct device *device); #endif diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 9125764844..22b9437149 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -223,11 +223,6 @@ void haswell_late_initialization(void); void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index b0e849020c..1f686d57b2 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -272,12 +272,6 @@ int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); -void report_platform_info(void); #endif /* !__SMM__ */ #endif diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8e6be2953e..b29dc6a069 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -213,12 +213,6 @@ void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); - #endif /* !__SMM__ */ void pch_enable_lpc(void); diff --git a/src/soc/intel/denverton_ns/include/soc/bootblock.h b/src/soc/intel/denverton_ns/include/soc/bootblock.h index 5136ecd494..6efedc36c3 100644 --- a/src/soc/intel/denverton_ns/include/soc/bootblock.h +++ b/src/soc/intel/denverton_ns/include/soc/bootblock.h @@ -22,12 +22,4 @@ //void bootblock_systemagent_early_init(void); void early_uart_init(void); -/* Bootblock post console init programming */ -//void enable_smbus(void); -//void i2c_early_init(void); -//void pch_early_init(void); -//void report_platform_info(void); -//void report_memory_config(void); -//void set_max_freq(void); - #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 68bdd12cbf..34831b13bb 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -58,11 +58,6 @@ int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); void soc_enable(struct device *dev); -/* debugging functions */ -void print_pci_devices(void); -void dump_pci_device(unsigned dev); -void dump_pci_devices(void); -void dump_spd_registers(void); void report_platform_info(void); #endif /* __PRE_RAM__ */