mb/supermicro: restructure x11ssh-tf to represent a x11 board series
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.
There are about 20 boards that can be added, if there is a community for
testing.
To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.
It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").
The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.
X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.
Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.
Documentation is reworked in CB:35547
Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner
Patrick Georgi
parent
b68ebfa8fc
commit
0a6c62fbbe
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@ -108,7 +108,7 @@ The boards in this section are not real mainboards, but emulators.
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## Supermicro
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- [X10SLM+-F](supermicro/x10slm-f.md)
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- [X11SSH-TF](supermicro/x11ssh-tf.md)
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- [X11 LGA1151 series](supermicro/x11-lga1151-series/index.md)
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## UP
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@ -0,0 +1,7 @@
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# X11 LGA1151 series
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The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor
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differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE,
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IPMI etc. This is why those boards are grouped as "X11 LGA1151 series".
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- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
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@ -15,7 +15,7 @@ The CH341 was found working, while Dediprog won't detect the chip.
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For more details have a look at the [flashing tutorial].
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The flash IC can be found between the two PCIe slots near the southbridge:
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## BMC (IPMI)
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@ -68,6 +68,6 @@ mainboard near the [AST2400]. This chip is an [MX25L25635F].
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[flashrom]: https://flashrom.org/Flashrom
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[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
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[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
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[flashing tutorial]: ../../flash_tutorial/ext_power.md
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[Intel FSP2.0]: ../../soc/intel/fsp/index.md
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[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
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[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
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[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
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Before Width: | Height: | Size: 135 KiB After Width: | Height: | Size: 135 KiB |
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@ -1,4 +1,4 @@
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config BOARD_SUPERMICRO_BASEBOARD_X11SSH
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config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
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def_bool n
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_RESUME
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@ -12,7 +12,27 @@ config BOARD_SUPERMICRO_BASEBOARD_X11SSH
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select GENERATE_SMBIOS_TABLES
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select IPMI_KCS
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if BOARD_SUPERMICRO_BASEBOARD_X11SSH
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if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
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config MAINBOARD_FAMILY
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string
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default "Supermicro_X11_LGA1151_SERIES"
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config MAINBOARD_PART_NUMBER
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string
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default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF
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config MAINBOARD_DIR
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string
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default "supermicro/x11-lga1151-series"
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config VARIANT_DIR
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string
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default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config VBOOT
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select VBOOT_NO_BOARD_SUPPORT
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@ -40,22 +60,6 @@ config IRQ_SLOT_COUNT
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int
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default 18
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config MAINBOARD_DIR
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string
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default "supermicro/x11ssh"
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config VARIANT_DIR
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string
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default "tf" if BOARD_SUPERMICRO_X11SSH_TF
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config MAINBOARD_PART_NUMBER
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string
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default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF
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config MAX_CPUS
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int
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default 8
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@ -76,4 +80,4 @@ config DIMM_SPD_SIZE
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int
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default 512
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endif # BOARD_SUPERMICRO_BASEBOARD_X11SSH
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endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
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@ -0,0 +1,3 @@
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config BOARD_SUPERMICRO_X11SSH_TF
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bool "X11SSH-TF"
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select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
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@ -0,0 +1,2 @@
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Category: server
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Vendor name: Supermicro
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@ -15,7 +15,7 @@
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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#include <superio/aspeed/common/aspeed.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <delay.h>
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@ -0,0 +1,240 @@
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# FSP Configuration
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register "SmbusEnable" = "1"
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register "ScsEmmcEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "SaGv" = "SaGv_Disabled"
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# Disable SGX
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register "sgx_enable" = "0" # SGX is broken in coreboot
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register "PrmrrSize" = "128 * MiB"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# SATA configuration
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register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
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register "EnableSata" = "1"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{ \
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[0] = 1, \
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[1] = 1, \
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[2] = 1, \
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[3] = 1, \
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[4] = 1, \
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[5] = 1, \
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[6] = 1, \
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[7] = 1, \
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}"
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register "SataPortsDevSlp" = "{\
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[0] = 0, \
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[1] = 0, \
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[2] = 0, \
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[3] = 0, \
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[4] = 0, \
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[5] = 0, \
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[6] = 0, \
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[7] = 0, \
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}"
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# superspeed_inter-chip_supplement (SSIC) disabled
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register "SsicPortEnable" = "0"
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# USB configuration
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# USB2/3
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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# ?
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register "usb2_ports[14]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[15]" = "USB2_PORT_MID(OC0)"
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# USB4/5
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register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
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# USB0/1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
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# USB9/10 (USB3.0)
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"
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register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
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# USB6/7 (USB3.0)
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register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
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# USB8 (USB3.0)
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register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
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# IPMI USB HUB
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
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# LPC
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
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register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
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register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
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register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
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# VR Settings Configuration for 4 Domains
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# ICC_MAX = 0 (Auto)
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# Voltage limit 1.52V (not used on KBL-S and KBL-DT)
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# Disable PS4 powerstate in S0ix, thus no package C10 support
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# psi threshold is using FSP default values
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0, \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0, \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0 ,\
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1, \
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.psi4enable = 0, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0, \
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.voltage_limit = 1520 \
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}"
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# No extra VR mailbox command
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register "SendVrMbxCmd" = "0"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 01.0 off end # CPU PCIe Port 10 (x16)
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device pci 01.1 off end # CPU PCIe Port 11 (x8)
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device pci 01.2 off end # CPU PCIe Port 12 (x4)
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device pci 02.0 off end # Integrated Graphics Device (IGD)
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device pci 04.0 on end # SA thermal subsystem
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device pci 05.0 off end # Imaging Unit
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device pci 08.0 off end # Gaussion Mixture Model (GMM)
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 19.0 off end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # I2C #4
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device pci 1b.0 off end # PCH PCIe Port 17
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device pci 1b.1 off end # PCH PCIe Port 18
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device pci 1b.2 off end # PCH PCIe Port 19
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device pci 1b.3 off end # PCH PCIe Port 20
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device pci 1c.0 off end # PCH PCIe Port 1
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device pci 1c.1 off end # PCH PCIe Port 2
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device pci 1c.2 off end # PCH PCIe Port 3
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device pci 1c.3 off end # PCH PCIe Port 4
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device pci 1c.4 off end # PCH PCIe Port 5
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device pci 1c.5 off end # PCH PCIe Port 6
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device pci 1c.6 off end # PCH PCIe Port 7
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device pci 1c.7 off end # PCH PCIe Port 8
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device pci 1d.0 off end # PCH PCIe Port 9
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device pci 1d.1 off end # PCH PCIe Port 10
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device pci 1d.2 off end # PCH PCIe Port 11
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device pci 1d.3 off end # PCH PCIe Port 12
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device pci 1d.4 off end # PCH PCIe Port 13
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device pci 1d.5 off end # PCH PCIe Port 14
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device pci 1d.6 off end # PCH PCIe Port 15
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device pci 1d.7 off end # PCH PCIe Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # SPI #0
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device pci 1f.0 on # LPC Interface
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chip superio/common
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device pnp 2e.0 on end
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end
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chip drivers/pc80/tpm # TPM
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 off end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI Controller
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device pci 1f.6 off end # GbE
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device pci 1f.7 off end # Intel Trace Hub
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end
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end
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@ -13,7 +13,7 @@
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#include <bootstate.h>
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#include <soc/ramstage.h>
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#include "gpio.h"
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#include <variant/gpio.h>
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void mainboard_silicon_init_params(FSP_SIL_UPD *params)
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{
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@ -1,6 +1,7 @@
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Category: server
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Vendor name: Supermicro
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Board name: X11SSH-TF
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Category: server
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Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -13,8 +13,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef _GPIOX11SSHTF_H
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#define _GPIOX11SSHTF_H
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#ifndef _GPIO_X11SSH_TF_H
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#define _GPIO_X11SSH_TF_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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@ -245,4 +245,4 @@ static const struct pad_config early_gpio_table[] = {
|
|||
};
|
||||
|
||||
#endif /* __ACPI__ */
|
||||
#endif /* _GPIOX11SSHTF_H */
|
||||
#endif /* _GPIO_X11SSH_TF_H */
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
chip soc/intel/skylake
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_B"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
|
||||
register "gen1_dec" = "0x007c0a01" # Super IO SWC
|
||||
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
|
||||
register "gen3_dec" = "0x000c03e1" # UART3
|
||||
register "gen4_dec" = "0x000c02e1" # UART4
|
||||
|
||||
# PCIe configuration
|
||||
# Enable JPCIE1
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpClkReqSupport[0]" = "0"
|
||||
|
||||
# Enable ASpeed PCI bridge
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpClkReqSupport[2]" = "0"
|
||||
|
||||
# Enable X550T (10GbE)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpClkReqSupport[4]" = "0"
|
||||
|
||||
# Enable M.2
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpClkReqSupport[8]" = "0"
|
||||
|
||||
device domain 0 on
|
||||
device pci 01.0 on end # unused
|
||||
device pci 01.1 on # PCIE Slot (JPCIE1)
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
|
||||
end
|
||||
device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1)
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
|
||||
end
|
||||
device pci 1c.2 on # PCI Express Port 3
|
||||
device pci 00.0 on # Aspeed PCI Bridge
|
||||
device pci 00.0 on end # Aspeed 2400 VGA
|
||||
end
|
||||
end
|
||||
device pci 1c.4 on # PCI Express Port 5
|
||||
device pci 00.0 on end # 10GbE
|
||||
device pci 00.1 on end # 10GbE
|
||||
end
|
||||
device pci 1d.0 on # PCI Express Port 9
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
|
||||
end
|
||||
device pci 1f.0 on # LPC Interface
|
||||
chip drivers/ipmi
|
||||
# On cold boot it takes a while for the BMC to start the IPMI service
|
||||
register "wait_for_bmc" = "1"
|
||||
register "bmc_boot_timeout" = "60"
|
||||
device pnp ca2.0 on end # IPMI KCS
|
||||
end
|
||||
chip superio/common
|
||||
device pnp 2e.0 on
|
||||
chip superio/aspeed/ast2400
|
||||
device pnp 2e.2 on # SUART1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # SUART2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 on # SWC
|
||||
io 0x60 = 0xa00
|
||||
io 0x62 = 0xa10
|
||||
io 0x64 = 0xa20
|
||||
io 0x66 = 0xa30
|
||||
irq 0x70 = 0xb
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 0xc
|
||||
end
|
||||
device pnp 2e.7 on end # GPIO
|
||||
device pnp 2e.b on # SUART3
|
||||
io 0x60 = 0x3e8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.c on # SUART4
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.d on end # iLPC2AHB
|
||||
device pnp 2e.e on # Mailbox
|
||||
io 0x60 = 0xa40
|
||||
irq 0x70 = 0x00
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
config BOARD_SUPERMICRO_X11SSH_TF
|
||||
bool "X11SSH-TF"
|
||||
select BOARD_SUPERMICRO_BASEBOARD_X11SSH
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
Vendor name: Supermicro
|
||||
Board name: X11SSH Baseboard
|
||||
Category: server
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
|
|
@ -1,290 +0,0 @@
|
|||
chip soc/intel/skylake
|
||||
|
||||
# Enable deep Sx states
|
||||
register "deep_s5_enable_ac" = "0"
|
||||
register "deep_s5_enable_dc" = "0"
|
||||
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_B"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
|
||||
register "gen1_dec" = "0x007c0a01" # Super IO SWC
|
||||
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
|
||||
register "gen3_dec" = "0x000c03e1" # UART3
|
||||
register "gen4_dec" = "0x000c02e1" # UART4
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# FSP Configuration
|
||||
register "SmbusEnable" = "1"
|
||||
register "ScsEmmcEnabled" = "0"
|
||||
register "ScsEmmcHs400Enabled" = "0"
|
||||
register "ScsSdCardEnabled" = "0"
|
||||
register "SkipExtGfxScan" = "1"
|
||||
register "Device4Enable" = "1"
|
||||
register "SaGv" = "SaGv_Disabled"
|
||||
|
||||
# Disable SGX
|
||||
register "sgx_enable" = "0" # SGX is broken in coreboot
|
||||
register "PrmrrSize" = "128 * MiB"
|
||||
|
||||
register "pirqa_routing" = "PCH_IRQ11"
|
||||
register "pirqb_routing" = "PCH_IRQ10"
|
||||
register "pirqc_routing" = "PCH_IRQ11"
|
||||
register "pirqd_routing" = "PCH_IRQ11"
|
||||
register "pirqe_routing" = "PCH_IRQ11"
|
||||
register "pirqf_routing" = "PCH_IRQ11"
|
||||
register "pirqg_routing" = "PCH_IRQ11"
|
||||
register "pirqh_routing" = "PCH_IRQ11"
|
||||
|
||||
# SATA configuration
|
||||
register "SataMode" = "0" # AHCI
|
||||
register "EnableSata" = "1"
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataPortsEnable" = "{ \
|
||||
[0] = 1, \
|
||||
[1] = 1, \
|
||||
[2] = 1, \
|
||||
[3] = 1, \
|
||||
[4] = 1, \
|
||||
[5] = 1, \
|
||||
[6] = 1, \
|
||||
[7] = 1, \
|
||||
}"
|
||||
|
||||
register "SataPortsDevSlp" = "{\
|
||||
[0] = 0, \
|
||||
[1] = 0, \
|
||||
[2] = 0, \
|
||||
[3] = 0, \
|
||||
[4] = 0, \
|
||||
[5] = 0, \
|
||||
[6] = 0, \
|
||||
[7] = 0, \
|
||||
}"
|
||||
|
||||
# superspeed_inter-chip_supplement (SSIC) disabled
|
||||
register "SsicPortEnable" = "0"
|
||||
|
||||
# USB configuration
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2/3
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2/3
|
||||
register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # ?
|
||||
register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # ?
|
||||
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB4/5
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB4/5
|
||||
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB0/1
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # USB0/1
|
||||
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
|
||||
register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
|
||||
|
||||
register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
|
||||
register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
|
||||
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # USB8 (USB3.0)
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
|
||||
|
||||
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB
|
||||
|
||||
# LPC
|
||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||
|
||||
# PCIe configuration
|
||||
# Enable JPCIE1
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpClkReqSupport[0]" = "0"
|
||||
|
||||
# Enable ASpeed PCI bridge
|
||||
register "PcieRpEnable[2]" = "1"
|
||||
register "PcieRpClkReqSupport[2]" = "0"
|
||||
|
||||
# Enable X550T (10GbE)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpClkReqSupport[4]" = "0"
|
||||
|
||||
# Enable M.2
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpClkReqSupport[8]" = "0"
|
||||
|
||||
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
|
||||
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
|
||||
register "PmConfigSlpS3MinAssert" = "0x02"
|
||||
|
||||
# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
|
||||
register "PmConfigSlpS4MinAssert" = "0x04"
|
||||
|
||||
# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
|
||||
register "PmConfigSlpSusMinAssert" = "0x03"
|
||||
|
||||
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
|
||||
register "PmConfigSlpAMinAssert" = "0x03"
|
||||
|
||||
# VR Settings Configuration for 4 Domains
|
||||
# ICC_MAX = 0 (Auto)
|
||||
# Voltage limit 1.52V (not used on KBL-S and KBL-DT)
|
||||
# Disable PS4 powerstate in S0ix, thus no package C10 support
|
||||
# psi threshold is using FSP default values
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 0, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0, \
|
||||
.voltage_limit = 1520 \
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 0, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0, \
|
||||
.voltage_limit = 1520 \
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 0, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0 ,\
|
||||
.voltage_limit = 1520 \
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 0, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0, \
|
||||
.voltage_limit = 1520 \
|
||||
}"
|
||||
|
||||
# No extra VR mailbox command
|
||||
register "SendVrMbxCmd" = "0"
|
||||
|
||||
# Lock Down
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 01.0 on end # unused
|
||||
device pci 01.1 on
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
|
||||
end # PCIE Slot (JPCIE1)
|
||||
device pci 04.0 on end # SA thermal subsystem
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Thermal Subsystem
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 on end # Management Engine Interface 2
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 1c.0 on
|
||||
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
|
||||
end # PCI Express Port 1 (Slot JPCIE1)
|
||||
device pci 1c.2 on
|
||||
device pci 00.0 on
|
||||
device pci 00.0 on end # Aspeed 2400 VGA
|
||||
end
|
||||
end # PCI Express Port 3
|
||||
device pci 1c.4 on
|
||||
device pci 00.0 on end # 10GbE
|
||||
device pci 00.1 on end # 10GbE
|
||||
end # PCI Express Port 5
|
||||
device pci 1d.0 on
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
|
||||
end # PCI Express Port 9
|
||||
device pci 1f.0 on
|
||||
chip drivers/ipmi
|
||||
# On cold boot it takes a while for the BMC to start the IPMI service
|
||||
register "wait_for_bmc" = "1"
|
||||
register "bmc_boot_timeout" = "60"
|
||||
device pnp ca2.0 on end # IPMI KCS
|
||||
end
|
||||
chip superio/common
|
||||
device pnp 2e.0 on
|
||||
chip superio/aspeed/ast2400
|
||||
device pnp 2e.2 on # SUART1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # SUART2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 on # SWC
|
||||
io 0x60 = 0xa00
|
||||
io 0x62 = 0xa10
|
||||
io 0x64 = 0xa20
|
||||
io 0x66 = 0xa30
|
||||
irq 0x70 = 0xb
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 0xc
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
end
|
||||
device pnp 2e.b on # SUART3
|
||||
io 0x60 = 0x3e8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.c on # SUART4
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.d on # iLPC2AHB
|
||||
end
|
||||
device pnp 2e.e on # Mailbox
|
||||
io 0x60 = 0xa40
|
||||
irq 0x70 = 0x00
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # SPI Controller
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue