diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index a3c4c80d14..dad18e7ff7 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -8,6 +8,7 @@ chip soc/intel/cannonlake
 	register "SaGv" = "3"
 	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
+	register "ScsEmmcEnabled" = "1"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index a3c4c80d14..dad18e7ff7 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -8,6 +8,7 @@ chip soc/intel/cannonlake
 	register "SaGv" = "3"
 	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
+	register "ScsEmmcEnabled" = "1"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge