From 0a712c33379799b13215068e4dcbad8272d38ccc Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 5 Sep 2017 17:09:30 -0700 Subject: [PATCH] mainboard/intel/cannonlake_rvp: enable eMMC Set SCS emmc enable FSP parameter. Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/21409 Reviewed-by: Lijian Zhao Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Pratikkumar V Prajapati --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 1 + src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index a3c4c80d14..dad18e7ff7 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -8,6 +8,7 @@ chip soc/intel/cannonlake register "SaGv" = "3" register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index a3c4c80d14..dad18e7ff7 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -8,6 +8,7 @@ chip soc/intel/cannonlake register "SaGv" = "3" register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" device domain 0 on device pci 00.0 on end # Host Bridge