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Intel model_106cx: change CAR to HT-capable 

There are hyper-threading Atom CPUs, those would not enable L2
cache with model_6ex CAR code. Switch to code that can handle
different number of threads and cores.

Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1384
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: James Laird <jhl@mafipulation.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2012-07-31 23:47:09 +03:00 committed by Alexandru Gagniuc
parent c33f1e9261
commit 0a78f91fa3
2 changed files with 2 additions and 1 deletions
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1
src/cpu/intel/model_106cx/Kconfig
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@ -3,6 +3,7 @@ config CPU_INTEL_MODEL_106CX
select SMP select SMP
select SSE2 select SSE2
select UDELAY_LAPIC select UDELAY_LAPIC
select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE

2
src/cpu/intel/model_106cx/Makefile.inc
View File

@ -1,4 +1,4 @@
driver-y += model_106cx_init.c driver-y += model_106cx_init.c
subdirs-y += ../../x86/name subdirs-y += ../../x86/name
cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc