Intel model_106cx: change CAR to HT-capable
There are hyper-threading Atom CPUs, those would not enable L2 cache with model_6ex CAR code. Switch to code that can handle different number of threads and cores. Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1384 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: James Laird <jhl@mafipulation.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
parent
c33f1e9261
commit
0a78f91fa3
|
@ -3,6 +3,7 @@ config CPU_INTEL_MODEL_106CX
|
|||
select SMP
|
||||
select SSE2
|
||||
select UDELAY_LAPIC
|
||||
select SIPI_VECTOR_IN_ROM
|
||||
select AP_IN_SIPI_WAIT
|
||||
select TSC_SYNC_MFENCE
|
||||
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
driver-y += model_106cx_init.c
|
||||
subdirs-y += ../../x86/name
|
||||
|
||||
cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
|
||||
cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc
|
||||
|
|
Loading…
Reference in New Issue