cpu/intel/car/cache_as_ram.inc: Fix long standing issues
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE for consistency. Do not set %ebp before and switch directly to stack returned by romstage_main(). Remove an unneeded 4-byte gap in CAR stack. The caching strategy for flash XIP area should be WRPROT. Clarify the various comments in the file on the logic. Together they lay the groundwork for bringing EARLY_CBMEM_INIT to intel/slot_1 boards. Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21503 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui
Kyösti Mälkki
parent
5036ebd190
commit
0a9982f3fb
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@ -22,9 +22,6 @@
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#include <cpu/x86/lapic_def.h>
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#include <cpu/x86/post_code.h>
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#define CacheSize CONFIG_DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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/* Save the BIST result. */
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movl %eax, %ebp
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@ -128,32 +125,29 @@ clear_fixed_var_mtrr_out:
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*/
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.endm
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#if CacheSize > 0x10000
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#if CONFIG_DCACHE_RAM_SIZE > 0x10000
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#error Invalid CAR size, must be at most 64k.
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#endif
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#if CacheSize < 0x1000
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#if CONFIG_DCACHE_RAM_SIZE < 0x1000
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#error Invalid CAR size, must be at least 4k. This is a processor limitation.
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#endif
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#if (CacheSize & (0x1000 - 1))
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#if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1))
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#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
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#endif
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#if CacheSize > 0x8000
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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/* Enable caching for 32K-64K using fixed MTRR. */
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movl $MTRR_FIX_4K_C0000, %ecx
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simplemask CacheSize, 0x8000
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simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000
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wrmsr
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#endif
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/* Enable caching for 0-32K using fixed MTRR. */
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movl $MTRR_FIX_4K_C8000, %ecx
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simplemask CacheSize, 0
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simplemask CONFIG_DCACHE_RAM_SIZE, 0
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wrmsr
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/*
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* Enable write base caching so we can do execute in place (XIP)
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* on the flash ROM.
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*/
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/* Enable cache for our code in Flash because we do XIP here. */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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/*
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@ -162,7 +156,7 @@ clear_fixed_var_mtrr_out:
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*/
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movl $copy_and_run, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRBACK, %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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@ -175,33 +169,31 @@ clear_fixed_var_mtrr_out:
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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/* Read the range with lodsl. */
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movl $CacheBase, %esi
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/* Read the CAR region. This will also fill up the cache.
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* IMPORTANT: This step is mandatory.
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*/
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movl $CONFIG_DCACHE_RAM_BASE, %esi
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cld
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movl $(CacheSize >> 2), %ecx
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movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
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rep lodsl
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/* Clear the range. */
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movl $CacheBase, %edi
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movl $(CacheSize >> 2), %ecx
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/* Clear the CAR region. */
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movl $CONFIG_DCACHE_RAM_BASE, %edi
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movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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movl $(CacheBase + CacheSize - 4), %eax
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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lout:
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/* Restore the BIST result. */
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movl %ebp, %eax
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/* We need to set EBP? No need. */
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movl %esp, %ebp
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pushl %eax /* BIST */
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call romstage_main
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/* Save return value from romstage_main. It contains the stack to use
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* after cache-as-ram is torn down.
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*/
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movl %eax, %ebx
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/* Setup stack as indicated by return value from romstage_main(). */
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movl %eax, %esp
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/* We don't need CAR from now on. */
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@ -210,7 +202,7 @@ lout:
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Clear sth. */
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/* Clear the fixed MTRR we used. */
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movl $MTRR_FIX_4K_C8000, %ecx
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xorl %edx, %edx
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xorl %eax, %eax
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@ -222,12 +214,12 @@ lout:
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#endif
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/*
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* Set the default memory type and disable fixed
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* and enable variable MTRRs.
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* Enable variable and disable fixed MTRRs.
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* Default memory type will be UC.
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*/
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movl $MTRR_DEF_TYPE_MSR, %ecx
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xorl %edx, %edx
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movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */
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movl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable cache. */
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@ -238,10 +230,6 @@ lout:
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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/* Setup stack as indicated by return value from romstage_main(). */
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movl %ebx, %esp
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movl %esp, %ebp
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call copy_and_run
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.Lhlt:
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