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cpu/intel/car/cache_as_ram.inc: Fix long standing issues 

Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE
and CONFIG_DCACHE_RAM_SIZE for consistency.

Do not set %ebp before and switch directly to stack returned by
romstage_main().

Remove an unneeded 4-byte gap in CAR stack.

The caching strategy for flash XIP area should be WRPROT.

Clarify the various comments in the file on the logic.

Together they lay the groundwork for bringing EARLY_CBMEM_INIT to
intel/slot_1 boards.

Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21503
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui 2017-09-11 18:41:16 -04:00 committed by Kyösti Mälkki
parent 5036ebd190
commit 0a9982f3fb
1 changed files with 23 additions and 35 deletions
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58
src/cpu/intel/car/cache_as_ram.inc
View File

@ -22,9 +22,6 @@
#include <cpu/x86/lapic_def.h> #include <cpu/x86/lapic_def.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
/* Save the BIST result. */ /* Save the BIST result. */
movl %eax, %ebp movl %eax, %ebp
@ -128,32 +125,29 @@ clear_fixed_var_mtrr_out:
*/ */
.endm .endm
#if CacheSize > 0x10000 #if CONFIG_DCACHE_RAM_SIZE > 0x10000
#error Invalid CAR size, must be at most 64k. #error Invalid CAR size, must be at most 64k.
#endif #endif
#if CacheSize < 0x1000 #if CONFIG_DCACHE_RAM_SIZE < 0x1000
#error Invalid CAR size, must be at least 4k. This is a processor limitation. #error Invalid CAR size, must be at least 4k. This is a processor limitation.
#endif #endif
#if (CacheSize & (0x1000 - 1)) #if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1))
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
#endif #endif
#if CacheSize > 0x8000 #if CONFIG_DCACHE_RAM_SIZE > 0x8000
/* Enable caching for 32K-64K using fixed MTRR. */ /* Enable caching for 32K-64K using fixed MTRR. */
movl $MTRR_FIX_4K_C0000, %ecx movl $MTRR_FIX_4K_C0000, %ecx
simplemask CacheSize, 0x8000 simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000
wrmsr wrmsr
#endif #endif
/* Enable caching for 0-32K using fixed MTRR. */ /* Enable caching for 0-32K using fixed MTRR. */
movl $MTRR_FIX_4K_C8000, %ecx movl $MTRR_FIX_4K_C8000, %ecx
simplemask CacheSize, 0 simplemask CONFIG_DCACHE_RAM_SIZE, 0
wrmsr wrmsr
/* /* Enable cache for our code in Flash because we do XIP here. */
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
/* /*
@ -162,7 +156,7 @@ clear_fixed_var_mtrr_out:
*/ */
movl $copy_and_run, %eax movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
@ -175,33 +169,31 @@ clear_fixed_var_mtrr_out:
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl. */ /* Read the CAR region. This will also fill up the cache.
movl $CacheBase, %esi * IMPORTANT: This step is mandatory.
*/
movl $CONFIG_DCACHE_RAM_BASE, %esi
cld cld
movl $(CacheSize >> 2), %ecx movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
rep lodsl rep lodsl
/* Clear the range. */ /* Clear the CAR region. */
movl $CacheBase, %edi movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $(CacheSize >> 2), %ecx movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
movl $(CacheBase + CacheSize - 4), %eax movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp movl %eax, %esp
lout: lout:
/* Restore the BIST result. */ /* Restore the BIST result. */
movl %ebp, %eax movl %ebp, %eax
/* We need to set EBP? No need. */
movl %esp, %ebp
pushl %eax /* BIST */ pushl %eax /* BIST */
call romstage_main call romstage_main
/* Save return value from romstage_main. It contains the stack to use /* Setup stack as indicated by return value from romstage_main(). */
* after cache-as-ram is torn down. movl %eax, %esp
*/
movl %eax, %ebx
/* We don't need CAR from now on. */ /* We don't need CAR from now on. */
@ -210,7 +202,7 @@ lout:
orl $CR0_CacheDisable, %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Clear sth. */ /* Clear the fixed MTRR we used. */
movl $MTRR_FIX_4K_C8000, %ecx movl $MTRR_FIX_4K_C8000, %ecx
xorl %edx, %edx xorl %edx, %edx
xorl %eax, %eax xorl %eax, %eax
@ -222,12 +214,12 @@ lout:
#endif #endif
/* /*
* Set the default memory type and disable fixed * Enable variable and disable fixed MTRRs.
* and enable variable MTRRs. * Default memory type will be UC.
*/ */
movl $MTRR_DEF_TYPE_MSR, %ecx movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */ movl $MTRR_DEF_TYPE_EN, %eax
wrmsr wrmsr
/* Enable cache. */ /* Enable cache. */
@ -238,10 +230,6 @@ lout:
__main: __main:
post_code(POST_PREPARE_RAMSTAGE) post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */ cld /* Clear direction flag. */
/* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
movl %esp, %ebp
call copy_and_run call copy_and_run
.Lhlt: .Lhlt: