sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
parent
398e84c71a
commit
0aa37c488b
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@ -139,9 +139,9 @@ properly, as it defines topology and chips that can be defined no other way.
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Let's go through the tree.
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\begin{verbatim}
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_F
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device apic 0 on end
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device lapic 0 on end
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end
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end
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\end{verbatim}
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@ -153,11 +153,11 @@ somewhere, since it runs memory.
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What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
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CPU socket. So the tree is rooted at the northbridge, which has a link to an apic cluster, and then the CPU. The CPU contains
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CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains
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its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
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{\it northbridge/amd/amdk8/root\_complex}, with its own apic\_cluster device which we turn on,
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{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on,
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which connects to a {\it cpu/amd/socket\_F},
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which has an apic, which is on.
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which has a local apic, which is on.
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Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
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is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
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@ -146,7 +146,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
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for (cpu = all_devices; cpu; cpu = cpu->next) {
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if ((cpu->path.type != DEVICE_PATH_APIC) ||
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(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
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(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
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continue;
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}
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if (!cpu->enabled)
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@ -152,7 +152,7 @@ void smp_write_processors(struct mp_config_table *mc)
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for(cpu = all_devices; cpu; cpu = cpu->next) {
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unsigned long cpu_flag;
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if ((cpu->path.type != DEVICE_PATH_APIC) ||
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(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
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(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
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{
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continue;
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}
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@ -194,7 +194,7 @@ static void enable_dev(struct device *dev)
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/* This is never hit as none of the sc520 boards have
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* an APIC cluster defined
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*/
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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#endif
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@ -48,7 +48,7 @@ static int determine_total_number_of_cores(void)
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int count = 0;
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for(cpu = all_devices; cpu; cpu = cpu->next) {
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if ((cpu->path.type != DEVICE_PATH_APIC) ||
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(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
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(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
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continue;
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}
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if (!cpu->enabled) {
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@ -209,9 +209,9 @@ const char *dev_path(device_t dev)
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sprintf(buffer, "DOMAIN: %04x",
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dev->path.domain.domain);
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break;
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case DEVICE_PATH_APIC_CLUSTER:
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sprintf(buffer, "APIC_CLUSTER: %01x",
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dev->path.apic_cluster.cluster);
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case DEVICE_PATH_CPU_CLUSTER:
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sprintf(buffer, "CPU_CLUSTER: %01x",
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dev->path.cpu_cluster.cluster);
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break;
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case DEVICE_PATH_CPU:
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sprintf(buffer, "CPU: %02x", dev->path.cpu.id);
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@ -274,9 +274,9 @@ int path_eq(struct device_path *path1, struct device_path *path2)
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case DEVICE_PATH_DOMAIN:
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equal = (path1->domain.domain == path2->domain.domain);
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break;
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case DEVICE_PATH_APIC_CLUSTER:
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equal = (path1->apic_cluster.cluster
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== path2->apic_cluster.cluster);
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case DEVICE_PATH_CPU_CLUSTER:
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equal = (path1->cpu_cluster.cluster
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== path2->cpu_cluster.cluster);
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break;
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case DEVICE_PATH_CPU:
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equal = (path1->cpu.id == path2->cpu.id);
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@ -859,7 +859,7 @@ int dev_count_cpu(void)
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for (cpu = all_devices; cpu; cpu = cpu->next) {
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if ((cpu->path.type != DEVICE_PATH_APIC) ||
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(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
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(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
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continue;
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if (!cpu->enabled)
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continue;
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@ -9,7 +9,7 @@ enum device_path_type {
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DEVICE_PATH_I2C,
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DEVICE_PATH_APIC,
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DEVICE_PATH_DOMAIN,
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DEVICE_PATH_APIC_CLUSTER,
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DEVICE_PATH_CPU_CLUSTER,
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DEVICE_PATH_CPU,
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DEVICE_PATH_CPU_BUS,
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DEVICE_PATH_IOAPIC,
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@ -50,7 +50,7 @@ struct ioapic_path
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unsigned ioapic_id;
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};
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struct apic_cluster_path
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struct cpu_cluster_path
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{
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unsigned cluster;
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};
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@ -69,15 +69,15 @@ struct cpu_bus_path
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struct device_path {
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enum device_path_type type;
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union {
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struct pci_path pci;
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struct pnp_path pnp;
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struct i2c_path i2c;
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struct apic_path apic;
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struct ioapic_path ioapic;
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struct domain_path domain;
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struct apic_cluster_path apic_cluster;
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struct cpu_path cpu;
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struct cpu_bus_path cpu_bus;
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struct pci_path pci;
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struct pnp_path pnp;
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struct i2c_path i2c;
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struct apic_path apic;
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struct ioapic_path ioapic;
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struct domain_path domain;
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struct cpu_cluster_path cpu_cluster;
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struct cpu_path cpu;
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struct cpu_bus_path cpu_bus;
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};
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};
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@ -1,5 +1,5 @@
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chip northbridge/intel/i440bx # Northbridge
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device lapic_cluster 0 on # APIC cluster
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device lapic 0 on end # APIC
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end
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@ -1,5 +1,5 @@
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chip northbridge/intel/i440bx # Northbridge
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device lapic_cluster 0 on # APIC cluster
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device lapic 0 on end # APIC
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end
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@ -65,7 +65,7 @@ chip northbridge/amd/lx
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/geode_lx
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device lapic 0 on end
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end
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@ -1,5 +1,5 @@
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chip northbridge/intel/i440bx # Northbridge
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device lapic_cluster 0 on # APIC cluster
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device lapic 0 on end # APIC
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end
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@ -1,6 +1,6 @@
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# sample config for advansus/A785E-I
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chip northbridge/amd/amdfam10/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_ASB2 #L1 and DDR3
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device lapic 0 on end
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end
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@ -1,6 +1,6 @@
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# sample config for amd/bimini_fam10
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chip northbridge/amd/amdfam10/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_ASB2 #L1 and DDR3
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device lapic 0 on end
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end
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@ -59,7 +59,7 @@ chip northbridge/amd/lx
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/geode_lx
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device lapic 0 on end
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end
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@ -9,7 +9,7 @@
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_S1G1
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device lapic 0 on end
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end
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@ -18,7 +18,7 @@
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#
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chip northbridge/amd/agesa/family15/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family15
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device lapic 0x20 on end
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end
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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@ -9,7 +9,7 @@
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_AM2
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device lapic 0 on end
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end
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@ -1,6 +1,6 @@
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# sample config for amd/mahogany_fam10
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chip northbridge/amd/amdfam10/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_AM2r2 #L1 and DDR2
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device lapic 0 on end
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end
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@ -32,7 +32,7 @@ chip northbridge/amd/lx
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/geode_lx
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device lapic 0 on end
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end
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@ -18,7 +18,7 @@
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#
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chip northbridge/amd/agesa/family15tn/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family15tn
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device lapic 10 on end
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end
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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@ -9,7 +9,7 @@
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_AM2
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device lapic 0 on end
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end
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@ -1,5 +1,5 @@
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chip northbridge/amd/gx2
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/geode_gx2
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device lapic 0 on end
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end
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@ -1,5 +1,5 @@
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chip northbridge/amd/amdk8/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_F
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device lapic 0 on end
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end
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@ -1,5 +1,5 @@
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chip northbridge/amd/amdfam10/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_F_1207 #L1 and DDR2
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device lapic 0 on end
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end
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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@ -18,7 +18,7 @@
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#
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chip northbridge/amd/agesa/family15tn/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family15tn
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device lapic 10 on end
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end
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@ -1,6 +1,6 @@
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# sample config for amd/tilapia_fam10
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chip northbridge/amd/amdfam10/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_AM3 #L1 and DDR3
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device lapic 0 on end
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end
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family12/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family12
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device lapic 0 on end
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end
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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@ -21,7 +21,7 @@
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chip northbridge/intel/e7505
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/intel/socket_mPGA604
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device lapic 0 on end
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device lapic 6 on end
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@ -1,5 +1,5 @@
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chip northbridge/amd/amdk8/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_940
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device lapic 0 on end
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end
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@ -32,7 +32,7 @@ chip northbridge/amd/lx
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/geode_lx
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device lapic 0 on end
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end
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@ -10,7 +10,7 @@
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#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
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#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
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chip northbridge/amd/amdk8/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/socket_939
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device lapic 0 on end
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end
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family14/root_complex
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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@ -1,5 +1,5 @@
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chip northbridge/amd/amdk8/root_complex # Root complex
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device lapic_cluster 0 on # (L)APIC cluster
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device cpu_cluster 0 on # (L)APIC cluster
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chip cpu/amd/socket_939 # CPU socket
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device lapic 0 on end # Local APIC of the CPU
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end
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@ -1,5 +1,5 @@
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chip northbridge/amd/amdk8/root_complex # Root complex
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device lapic_cluster 0 on # APIC cluster
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device cpu_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # CPU
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device lapic 0 on end # APIC
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end
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@ -1,5 +1,5 @@
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chip northbridge/amd/amdk8/root_complex # Root complex
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device lapic_cluster 0 on # APIC cluster
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device cpu_cluster 0 on # APIC cluster
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chip cpu/amd/socket_939 # CPU
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device lapic 0 on end # APIC
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end
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@ -22,7 +22,7 @@
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chip northbridge/intel/i5000
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device lapic_cluster 0 on
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device cpu_cluster 0 on
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chip cpu/intel/socket_LGA771
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device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_754 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
##
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device lapic_cluster 0 on # (L)APIC cluster
|
||||
device cpu_cluster 0 on # (L)APIC cluster
|
||||
chip cpu/amd/socket_AM2 # CPU socket
|
||||
device lapic 0 on end # Local APIC of the CPU
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_AM2 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_AM2 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# sample config for advansus/A785E-I
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR3
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i82810 # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # (L)APIC cluster
|
||||
device cpu_cluster 0 on # (L)APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU socket 0
|
||||
device lapic 0 on end # Local APIC of CPU 0
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # (L)APIC cluster
|
||||
device cpu_cluster 0 on # (L)APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU socket 0
|
||||
device lapic 0 on end # Local APIC of CPU 0
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# sample config for avalue/EAX-785E
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR3
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -32,7 +32,7 @@ chip northbridge/amd/lx
|
|||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/geode_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -56,7 +56,7 @@ chip northbridge/via/cn700 # Northbridge
|
|||
device pci 12.0 on end # Ethernet
|
||||
end
|
||||
end
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/via/c7 # VIA C7
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -48,7 +48,7 @@ chip northbridge/intel/i855
|
|||
end
|
||||
end
|
||||
end
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA479M
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -76,7 +76,7 @@ chip northbridge/amd/lx
|
|||
end
|
||||
|
||||
# APIC cluster is late CPU init.
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/geode_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
##
|
||||
|
||||
chip northbridge/intel/i82810 # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -21,7 +21,7 @@
|
|||
|
||||
chip northbridge/intel/i945
|
||||
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mFCPGA478
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/intel/i440bx # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_1 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device lapic_cluster 0 on # (L)APIC cluster
|
||||
device cpu_cluster 0 on # (L)APIC cluster
|
||||
chip cpu/amd/socket_AM2 # CPU socket
|
||||
device lapic 0 on end # Local APIC of the CPU
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# sample config for gigabyte/ma785gm
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# sample config for gigabyte/ma785gmt
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR3
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# sample config for gigabyte/ma78gm
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM2r2 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -12,7 +12,7 @@ chip northbridge/intel/sandybridge
|
|||
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
|
||||
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
|
||||
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_rPGA989
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -15,7 +15,7 @@ chip northbridge/intel/sandybridge
|
|||
register "gpu_cpu_backlight" = "0x000001d4"
|
||||
register "gpu_pch_backlight" = "0x03aa0000"
|
||||
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_rPGA989
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_F_1207
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# TODO: i810E actually!
|
||||
chip northbridge/intel/i82810 # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
chip northbridge/intel/i945
|
||||
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mFCPGA478
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# Config for iei/kino-780am2-fam10
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM2r2 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -67,7 +67,7 @@ chip northbridge/amd/lx
|
|||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/geode_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -93,7 +93,7 @@ chip northbridge/amd/lx
|
|||
end
|
||||
|
||||
# APIC cluster is late CPU init.
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/geode_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -79,7 +79,7 @@ chip northbridge/amd/lx
|
|||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/geode_lx
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
##
|
||||
|
||||
chip northbridge/intel/i82810 # Northbridge
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_FC_PGA370 # CPU
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
|
||||
chip northbridge/intel/i945
|
||||
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_441
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -64,7 +64,7 @@ chip northbridge/intel/i3100
|
|||
device pci 1f.4 on end # Performance counters
|
||||
end
|
||||
end
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_BGA956
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -9,7 +9,7 @@ chip northbridge/intel/sandybridge
|
|||
# Enable DVI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_rPGA989
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -69,7 +69,7 @@ chip northbridge/intel/e7520
|
|||
register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
|
||||
end
|
||||
end
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -37,7 +37,7 @@ chip northbridge/intel/i3100
|
|||
device pci 1f.3 on end # SMBus
|
||||
end
|
||||
end
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA479M
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -47,7 +47,7 @@ chip northbridge/intel/i3100
|
|||
device pci 1f.4 on end # ?
|
||||
end
|
||||
end
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/ep80579
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -62,7 +62,7 @@ chip northbridge/intel/e7501
|
|||
device pci 1f.6 off end # AC97 Modem
|
||||
end # SB
|
||||
end # PCI domain
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
chip northbridge/intel/sch
|
||||
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_441
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
chip northbridge/amd/amdk8/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
|
@ -54,7 +54,7 @@ chip northbridge/via/cn700 # Northbridge
|
|||
device pci 12.0 on end # Ethernet
|
||||
end
|
||||
end
|
||||
device lapic_cluster 0 on # APIC cluster
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/via/c7 # VIA C7
|
||||
device lapic 0 on end # APIC
|
||||
end
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# sample config for jetway/PA78VM5
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_AM2r2 #L1 and DDR2
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
|
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Reference in New Issue