From 0acfe22380cb4046a5c1965bd53a95a7d376ab5c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 26 Mar 2021 13:08:23 +0100 Subject: [PATCH] nb/intel: Replace remaining BAR accessors These changes are not reproducible for some reason. Change-Id: I43b445b8af8871db87fb86747db8a35cec75716a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/51867 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/northbridge.c | 22 ++++--------------- .../intel/sandybridge/northbridge.c | 7 +----- 2 files changed, 5 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0cf29b84d6..fdaac7c311 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -442,15 +442,10 @@ static void northbridge_topology_init(void) const u32 eple_a[3] = { EPLE2A, EPLE3A, EPLE4A }; const u32 eple_d[3] = { EPLE2D, EPLE3D, EPLE4D }; - u32 reg32; - /* Set the CID1 Egress Port 0 Root Topology */ epbar_clrsetbits32(EPESD, 0xff << 16, 1 << 16); - reg32 = epbar_read32(EPLE1D); - reg32 &= ~(0xff << 16); - reg32 |= 1 | (1 << 16); - epbar_write32(EPLE1D, reg32); + epbar_clrsetbits32(EPLE1D, 0xff << 16, 1 | 1 << 16); epbar_write32(EPLE1A, CONFIG_FIXED_DMIBAR_MMIO_BASE); epbar_write32(EPLE1A + 4, 0); @@ -463,10 +458,7 @@ static void northbridge_topology_init(void) epbar_write32(eple_a[i], (u32)PCI_DEV(0, 1, i)); epbar_write32(eple_a[i] + 4, 0); - reg32 = epbar_read32(eple_d[i]); - reg32 &= ~(0xff << 16); - reg32 |= 1 | (1 << 16); - epbar_write32(eple_d[i], reg32); + epbar_clrsetbits32(eple_d[i], 0xff << 16, 1 | 1 << 16); pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); pci_write_config32(dev, PEG_LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE); @@ -480,19 +472,13 @@ static void northbridge_topology_init(void) /* Set the CID1 DMI Port Root Topology */ dmibar_clrsetbits32(DMIESD, 0xff << 16, 1 << 16); - reg32 = dmibar_read32(DMILE1D); - reg32 &= ~(0xffff << 16); - reg32 |= 1 | (2 << 16); - dmibar_write32(DMILE1D, reg32); + dmibar_clrsetbits32(DMILE1D, 0xffff << 16, 1 | 2 << 16); dmibar_write32(DMILE1A, CONFIG_FIXED_RCBA_MMIO_BASE); dmibar_write32(DMILE1A + 4, 0); dmibar_write32(DMILE2A, CONFIG_FIXED_EPBAR_MMIO_BASE); dmibar_write32(DMILE2A + 4, 0); - reg32 = dmibar_read32(DMILE2D); - reg32 &= ~(0xff << 16); - reg32 |= 1 | (1 << 16); - dmibar_write32(DMILE2D, reg32); + dmibar_clrsetbits32(DMILE2D, 0xff << 16, 1 | 1 << 16); /* Program RO and Write-Once Registers */ dmibar_setbits32(DMIPVCCAP1, 0); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 6e954611e1..bd4d1078da 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -210,8 +210,6 @@ static void northbridge_dmi_init(struct device *dev) const u8 stepping = cpu_stepping(); - u32 reg32; - /* Steps prior to DMI ASPM */ if (is_sandy) { dmibar_clrsetbits32(0x250, 7 << 20, 2 << 20); @@ -224,10 +222,7 @@ static void northbridge_dmi_init(struct device *dev) } if (!is_sandy || stepping >= SNB_STEP_D1) { - reg32 = dmibar_read32(0x1f8); - reg32 &= ~(1 << 26); - reg32 |= (1 << 16); - dmibar_write32(0x1f8, reg32); + dmibar_clrsetbits32(0x1f8, 1 << 26, 1 << 16); dmibar_setbits32(0x1fc, 1 << 12 | 1 << 23);