soc/qualcomm: Make sc7180 mdss configurations common code
This change makes mdss configuration common for both sc7180 & sc7280 to avoid code duplicacy. Changes in v2: - Move soc related mdss changes to soc specific disp.c BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: Ibc43ab6ee5ced08e34625e1485febd2f4717d6a0 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Vinod Polimera
Felix Held
parent
7aef2b1294
commit
0af24f7bb7
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@ -2,7 +2,9 @@
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#include <device/mmio.h>
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#include <console/console.h>
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#include <delay.h>
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#include <edid.h>
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#include <soc/clock.h>
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#include <soc/display/mdssreg.h>
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#define MDSS_MDP_MAX_PREFILL_FETCH 24
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@ -41,7 +43,7 @@ static void mdss_source_pipe_config(struct edid *edid)
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write32(&mdp_sspp->sspp_src_format, 0x000236ff);
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write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001);
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flip_bits |= BIT(31);
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flip_bits |= SW_PIX_EXT_OVERRIDE;
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write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size);
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write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size);
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write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size);
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@ -54,38 +56,11 @@ static void mdss_vbif_setup(void)
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write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333);
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}
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static void mdss_intf_tg_setup(struct edid *edid)
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{
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uint32_t hsync_period, vsync_period;
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uint32_t hsync_start_x, hsync_end_x;
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uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
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hsync_period = edid->mode.ha + edid->mode.hbl;
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vsync_period = edid->mode.va + edid->mode.vbl;
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hsync_start_x = edid->mode.hbl - edid->mode.hso;
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hsync_end_x = hsync_period - edid->mode.hso - 1;
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display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period;
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display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1;
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hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
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display_hctl = (hsync_end_x << 16) | hsync_start_x;
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write32(&mdp_intf->intf_hsync_ctl, hsync_ctl);
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write32(&mdp_intf->intf_vysnc_period_f0,
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vsync_period * hsync_period);
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write32(&mdp_intf->intf_vysnc_pulse_width_f0,
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edid->mode.vspw * hsync_period);
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write32(&mdp_intf->intf_disp_hctl, display_hctl);
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write32(&mdp_intf->intf_disp_v_start_f0, display_vstart);
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write32(&mdp_intf->intf_disp_v_end_f0, display_vend);
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write32(&mdp_intf->intf_underflow_color, 0x00);
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write32(&mdp_intf->intf_panel_format, 0x2100);
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}
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static void mdss_intf_fetch_start_config(struct edid *edid)
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{
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uint32_t v_total, h_total, fetch_start, vfp_start;
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uint32_t prefetch_avail, prefetch_needed;
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uint32_t fetch_enable = BIT(31);
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uint32_t fetch_enable = PROG_FETCH_START_EN;
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/*
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* MDP programmable fetch is for MDP with rev >= 1.05.
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@ -135,8 +110,8 @@ static void mdss_layer_mixer_setup(struct edid *edid)
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}
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/* Enable border fill */
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left_staging_level = BIT(24);
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left_staging_level |= BIT(1);
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left_staging_level = BORDER_OUT;
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left_staging_level |= VIG_0_OUT;
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/* Base layer for layer mixer 0 */
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write32(&mdp_ctl->ctl_layer0, left_staging_level);
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@ -172,12 +147,7 @@ void mdp_dsi_video_config(struct edid *edid)
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mdss_vbif_qos_remapper_setup();
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mdss_source_pipe_config(edid);
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mdss_layer_mixer_setup(edid);
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/* Select Video Mode Interface */
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write32(&mdp_ctl->ctl_top, 0x0);
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/* PPB0 to INTF1 */
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write32(&mdp_ctl->ctl_intf_active, BIT(1));
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mdss_ctrl_config();
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write32(&mdp_intf->intf_mux, 0x0F0000);
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}
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@ -186,6 +156,6 @@ void mdp_dsi_video_on(void)
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uint32_t ctl0_reg_val;
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ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF;
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write32(&mdp_ctl->ctl_intf_flush, 0x2);
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write32(&mdp_ctl->ctl_intf_flush, INTF_FLUSH);
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write32(&mdp_ctl->ctl_flush, ctl0_reg_val);
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}
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@ -45,7 +45,8 @@ ramstage-y += ../common/usb/qmpv3_usb_phy.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/disp.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/display/mdss.c
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################################################################################
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@ -0,0 +1,39 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/display/mdssreg.h>
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void mdss_intf_tg_setup(struct edid *edid)
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{
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uint32_t hsync_period, vsync_period, hsync_start_x, hsync_end_x;
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uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
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uint32_t mdss_version;
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mdss_version = read32(&mdss_hw->hw_version);
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hsync_period = edid->mode.ha + edid->mode.hbl;
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vsync_period = edid->mode.va + edid->mode.vbl;
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hsync_start_x = edid->mode.hbl - edid->mode.hso;
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hsync_end_x = hsync_period - edid->mode.hso - 1;
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display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period;
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display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1;
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hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
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display_hctl = (hsync_end_x << 16) | hsync_start_x;
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write32(&mdp_intf->intf_hsync_ctl, hsync_ctl);
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write32(&mdp_intf->intf_vysnc_period_f0, vsync_period * hsync_period);
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write32(&mdp_intf->intf_vysnc_pulse_width_f0, edid->mode.vspw * hsync_period);
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write32(&mdp_intf->intf_disp_hctl, display_hctl);
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write32(&mdp_intf->intf_disp_v_start_f0, display_vstart);
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write32(&mdp_intf->intf_disp_v_end_f0, display_vend);
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write32(&mdp_intf->intf_underflow_color, 0x00);
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write32(&mdp_intf->intf_panel_format, 0x2100);
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}
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void mdss_ctrl_config(void)
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{
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/* Select Video Mode Interface */
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write32(&mdp_ctl->ctl_top, 0x0);
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/* PPB0 to INTF1 */
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write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_1);
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}
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@ -4,6 +4,9 @@
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#define _SOC_DISPLAY_MDSS_REG_H_
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#include <types.h>
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#include <edid.h>
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#define INTF_FLUSH INTF_FLUSH_1
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struct dsi_regs {
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uint32_t hw_version;
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@ -235,7 +238,14 @@ struct mdp_intf_regs {
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uint32_t intf_active_hctl;
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uint32_t intf_border_color;
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uint32_t intf_underflow_color;
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uint32_t reserved0[17];
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uint32_t hsync_skew;
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uint32_t polarity_ctl;
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uint32_t test_ctl;
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uint32_t tp_color0;
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uint32_t tp_color1;
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uint32_t intf_config2;
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uint32_t display_data_hctl;
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uint32_t reserved0[10];
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uint32_t intf_panel_format;
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uint32_t reserved1[55];
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uint32_t intf_prof_fetch_start;
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@ -256,7 +266,9 @@ struct mdp_ctl_regs {
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uint32_t ctl_start;
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uint32_t reserved1[53];
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uint32_t ctl_intf_active;
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uint32_t reserved2[6];
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uint32_t ctl_cdm_active;
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uint32_t ctl_fetch_pipe_active; /* reserved for sc7180 */
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uint32_t reserved2[4];
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uint32_t ctl_intf_flush;
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};
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@ -308,6 +320,10 @@ check_member(mdp_sspp_regs, sspp_sw_pic_ext_c0_req_pixels, 0x108);
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check_member(mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118);
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check_member(mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128);
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struct mdss_hw_regs {
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uint32_t hw_version;
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};
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struct vbif_rt_regs {
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uint32_t reserved0[88];
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uint32_t vbif_out_axi_amemtype_conf0;
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@ -448,9 +464,57 @@ enum {
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BROADCAST_EN = BIT(31),
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};
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/* MDP_VP_0_VIG_0_SSPP_SRC_OP_MODE */
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enum {
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BWC_DEC_EN = BIT(0),
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SW_PIX_EXT_OVERRIDE = BIT(31),
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};
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/* MDP_INTF_x_INTF_CONFIG */
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enum {
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INTERLACE_MODE = BIT(0),
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REPEAT_PIXEL = BIT(1),
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INTERLACE_INIT_SEL = BIT(2),
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BORDER_ENABLE = BIT(3),
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EDP_PSR_OVERRIDE_EN = BIT(7),
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PACK_ALIGN = BIT(10),
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DSI_VIDEO_STOP_MODE = BIT(23),
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ACTIVE_H_EN = BIT(29),
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ACTIVE_V_EN = BIT(30),
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PROG_FETCH_START_EN = BIT(31),
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};
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/* MDP_CTL_0_LAYER_0 */
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enum {
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VIG_0_OUT = BIT(0),
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BORDER_OUT = BIT(24),
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};
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/* MDP_CTL_0_FETCH_PIPE_ACTIVE */
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enum {
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FETCH_PIPE_VIG0_ACTIVE = BIT(16),
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FETCH_PIPE_VIG1_ACTIVE = BIT(17),
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};
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/* MDP_CTL_0_INTF_ACTIVE*/
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enum {
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INTF_ACTIVE_0 = BIT(0),
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INTF_ACTIVE_1 = BIT(1),
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INTF_ACTIVE_5 = BIT(5),
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};
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/* MDP_CTL_0_INTF_FLUSH */
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enum {
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INTF_FLUSH_0 = BIT(0),
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INTF_FLUSH_1 = BIT(1),
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INTF_FLUSH_5 = BIT(5),
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};
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static struct dsi_regs *const dsi0 = (void *)DSI0_CTL_BASE;
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static struct dsi_phy_regs *const dsi0_phy = (void *)DSI0_PHY_BASE;
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static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM;
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static struct mdss_hw_regs *const mdss_hw = (void *)MDSS_BASE;
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static struct mdp_intf_regs *const mdp_intf = (void *)MDP_1_INTF_BASE;
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static struct mdp_ctl_regs *const mdp_ctl = (void *)MDP_0_CTL_BASE;
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static struct mdp_layer_mixer_regs *const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE;
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@ -458,6 +522,8 @@ static struct mdp_sspp_regs *const mdp_sspp = (void *)MDP_VP_0_SSPP_BASE;
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static struct vbif_rt_regs *const vbif_rt = (void *)MDP_VBIF_RT_BASE;
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void mdp_dsi_video_config(struct edid *edid);
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void mdss_intf_tg_setup(struct edid *edid);
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void mdp_dsi_video_on(void);
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void mdss_ctrl_config(void);
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#endif
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