Changes to allow Via/Epia code to be compiled after recent code changes.
New Files :- src/cpu/via/model_centaur/Config.lb src/cpu/via/model_centaur/model_centaur_init.c Updated Files :- src/arch/i386/include/arch/smp/mpspec.h - make write_smp_table a define for non smp systems src/cpu/x86/lapic/lapic_cpu_init.c - change possible typo src/mainboard/via/epia/Config.lb src/mainboard/via/epia/Options.lb src/mainboard/via/epia/auto.c src/mainboard/via/epia/chip.h src/mainboard/via/epia/failover.c - updated after recent code changes src/northbridge/via/vt8601/chip.h src/northbridge/via/vt8601/northbridge.c src/northbridge/via/vt8601/raminit.c - corrections after recent code changes to allow compiling src/southbridge/via/vt8231/chip.h src/southbridge/via/vt8231/vt8231.c - initial pass to allow compiling after recent code changes. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Mark Wilkinson
parent
97035448f3
commit
0afcba7a3d
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@ -267,11 +267,14 @@ void *smp_write_floating_table(unsigned long addr);
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unsigned long write_smp_table(unsigned long addr);
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#else /* HAVE_MP_TABLE */
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#if 0
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static inline
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unsigned long write_smp_table(unsigned long addr);
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unsigned long write_smp_table(unsigned long addr)
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{
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return addr;
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}
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#endif
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#define write_smp_table(addr) addr
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#endif /* HAVE_MP_TABLE */
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#endif
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@ -0,0 +1,9 @@
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dir /cpu/x86/tsc
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dir /cpu/x86/mtrr
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dir /cpu/x86/fpu
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dir /cpu/x86/mmx
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dir /cpu/x86/sse
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dir /cpu/x86/lapic
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dir /cpu/x86/cache
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dir /cpu/intel/microcode
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driver model_centaur_init.o
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@ -0,0 +1,56 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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static uint32_t microcode_updates[] = {
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/* WARNING - Intel has a new data structure that has variable length
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* microcode update lengths. They are encoded in int 8 and 9. A
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* dummy header of nulls must terminate the list.
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*/
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/* Dummy terminator */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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static void model_centaur_init(device_t dev)
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{
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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x86_mtrr_check();
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/* Update the microcode */
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intel_update_microcode(microcode_updates);
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/* Enable the local cpu apics */
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setup_lapic();
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};
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static struct device_operations cpu_dev_ops = {
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.init = model_centaur_init,
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};
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#warning "FIXME - need correct cpu id here for VIA C3"
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_CENTAUR, 0x0670 }, // VIA C3 Samual 2
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{ X86_VENDOR_CENTAUR, 0x0678 }, // VIA C3 Ezra
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{ X86_VENDOR_CENTAUR, 0x0680 }, // VIA C3 Ezra-T
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{ 0, 0 },
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};
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static struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -301,7 +301,7 @@ void initialize_cpus(struct bus *cpu_bus)
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cpu_path.u.apic.apic_id = lapicid();
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#else
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/* Get the device path of the boot cpu */
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cpu_path.type = DEVICE_PATH_BOOT_CPU;
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cpu_path.type = DEVICE_PATH_DEFAULT_CPU;
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#endif
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/* Find the device structure for the boot cpu */
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@ -14,9 +14,8 @@ end
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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@ -45,6 +44,7 @@ arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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@ -128,22 +128,21 @@ dir /pc80
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config chip.h
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chip northbridge/via/vt8601
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# pci 0:0.0
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# pci 0:1.0
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device pci_domain 0 on
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device pci 0.0 on
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chip southbridge/via/vt8231
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# pci 0:11.0
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# pci 0:11.1
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# pci 0:11.2
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# pci 0:11.3
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# pci 0:11.4
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# pci 0:11.5
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# pci 0:11.6
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# pci 0:12.0
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register "enable_usb" = "0"
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register "enable_native_ide" = "0"
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register "enable_com_ports" = "1"
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register "enable_keyboard" = "0"
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register "enable_nvram" = "1"
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device pci 11.0 on # Southbridge
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device pci 11.1 on end # Ide
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device pci 11.2 off end # Usb
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device pci 11.3 off end # Usb
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device pci 11.4 off end # ACPI
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device pci 11.5 off end # Audio
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device pci 11.6 on # Com
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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@ -177,10 +176,15 @@ chip northbridge/via/vt8601
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io 0x60 = 0x290
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end
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register "com1" = "{1}"
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# register "com1" = "{1, 0, 0x3f8, 4}"
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# register "lpt" = "{1}"
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end
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end
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device pci 12.0 on end # Ethernet
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end
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end
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end
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end
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chip cpu/via/model_centaur
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end
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end
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##
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@ -188,3 +192,4 @@ end
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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@ -68,6 +68,7 @@ default HAVE_OPTION_TABLE=1
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## Use a small 8K stack
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@ -87,4 +88,7 @@ default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_STREAM = 1
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end
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@ -2,7 +2,7 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <cpu/x86/lapic.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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@ -11,7 +11,7 @@
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/via/vt8601/raminit.h"
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#include "cpu/p6/earlymtrr.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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/*
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*/
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@ -23,7 +23,7 @@ void udelay(int usecs)
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}
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "debug.c"
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#include "southbridge/via/vt8231/vt8231_early_smbus.c"
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@ -96,8 +96,6 @@ static void enable_shadow_ram(void)
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static void main(void)
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{
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unsigned long x;
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/* init_timer();*/
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outb(5, 0x80);
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enable_vt8231_serial();
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@ -1,4 +1,4 @@
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extern struct chip_operations mainboard_via_epia_control;
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extern struct chip_operations mainboard_via_epia_ops;
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struct mainboard_via_epia_config {
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int nothing;
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@ -5,7 +5,7 @@
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#include <arch/io.h>
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#include "arch/romcc_io.h"
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#include "pc80/mc146818rtc_early.c"
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#include "cpu/p6/boot_cpu.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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static void main(void)
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{
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@ -7,8 +7,8 @@
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#include <arch/io.h>
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#include "chip.h"
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static int
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mainboard_scan_bus(device_t root, int maxbus)
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static unsigned int
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mainboard_scan_bus(device_t root, unsigned int maxbus)
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{
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int retval;
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printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
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@ -31,7 +31,7 @@ static void enable_dev(device_t dev)
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dev->ops = &mainboard_operations;
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}
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struct chip_operations mainboard_via_epia_control = {
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struct chip_operations mainboard_via_epia_ops = {
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.enable_dev = enable_dev,
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.name = "VIA EPIA mainboard ",
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};
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@ -2,4 +2,4 @@ struct northbridge_via_vt8601_config
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{
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};
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extern struct chip_operations northbridge_via_vt8601_control;
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extern struct chip_operations northbridge_via_vt8601_ops;
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@ -3,6 +3,7 @@
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/hypertransport.h>
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#include <stdlib.h>
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#include <string.h>
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@ -52,7 +53,6 @@ static struct pci_driver northbridge_driver __pci_driver = {
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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unsigned reg;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, 0);
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@ -133,7 +133,7 @@ static void pci_domain_set_resources(device_t dev)
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ramregs[i]);
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}
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printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
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tomk = ramreg*8*1024;
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tomk = rambits*8*1024;
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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@ -181,8 +181,6 @@ static struct device_operations cpu_bus_ops = {
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static void enable_dev(struct device *dev)
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{
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struct device_path path;
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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@ -192,7 +190,7 @@ static void enable_dev(struct device *dev)
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}
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}
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struct chip_operations northbridge_via_vt8601_control = {
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struct chip_operations northbridge_via_vt8601_ops = {
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.enable_dev = enable_dev,
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.name = "VIA vt8601 Northbridge",
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};
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@ -1,4 +1,4 @@
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#include <cpu/p6/mtrr.h>
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#include <cpu/x86/mtrr.h>
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#include "raminit.h"
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/*
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@ -1,7 +1,7 @@
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#ifndef _SOUTHBRIDGE_VIA_VT8231
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#define _SOUTHBRIDGE_VIA_VT8231
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extern struct chip_operations southbridge_via_vt8231_control;
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extern struct chip_operations southbridge_via_vt8231_ops;
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struct southbridge_via_vt8231_config {
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/* PCI function enables */
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@ -161,11 +161,9 @@ static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
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PCI slot is AD31 (device 15) (00:14.0)
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Southbridge is AD28 (device 12) (00:11.0)
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*/
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static void pci_routing_fixup(void)
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static void pci_routing_fixup(struct device *dev)
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{
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device_t dev;
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dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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printk_info("%s: dev is %p\n", __FUNCTION__, dev);
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if (dev) {
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/* initialize PCI interupts - these assignments depend
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@ -423,33 +421,21 @@ static void vt8231_init(struct southbridge_via_vt8231_config *conf)
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rtc_init(0);
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}
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static void southbridge_init(struct chip *chip, enum chip_pass pass)
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{
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struct southbridge_via_vt8231_config *conf =
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(struct southbridge_via_vt8231_config *)chip->chip_info;
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switch (pass) {
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case CONF_PASS_PRE_PCI:
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vt8231_pci_enable(conf);
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break;
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case CONF_PASS_POST_PCI:
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vt8231_init(conf);
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pci_routing_fixup();
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break;
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case CONF_PASS_PRE_BOOT:
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dump_south();
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break;
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default:
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/* nothing yet */
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break;
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}
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static void southbridge_init(struct device *dev) {
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vt8231_init(dev->chip_info);
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pci_routing_fixup(dev);
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}
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struct chip_operations southbridge_via_vt8231_control = {
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.enable = southbridge_init,
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struct device_operations vt8231_dev_ops = {
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.init = &southbridge_init,
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};
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static void southbridge_enable(struct device *dev)
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{
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dev->ops = &vt8231_dev_ops;
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}
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struct chip_operations southbridge_via_vt8231_ops = {
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.enable_dev = southbridge_enable,
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.name = "VIA vt8231"
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};
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