From 0b07e36a1fb7e48dc31aa6b630e3f7069a23e259 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Thu, 1 Jun 2023 23:22:11 +0200
Subject: [PATCH] soc/amd/stoneyridge/acpi: rename sb_fch.asl to mmio.asl

This file only contain the ACPI code describing the MMIO devices in the
FCH, so rename it to mmio.asl. This also brings the Stoneyridge ACPI
code a bit more in line with the ACPI code of the other SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iccef1fc5230e3e104d8dea586a9cbaf894471c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75597
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/stoneyridge/acpi/{sb_fch.asl => mmio.asl} | 0
 src/soc/amd/stoneyridge/acpi/soc.asl                  | 4 ++--
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename src/soc/amd/stoneyridge/acpi/{sb_fch.asl => mmio.asl} (100%)

diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/mmio.asl
similarity index 100%
rename from src/soc/amd/stoneyridge/acpi/sb_fch.asl
rename to src/soc/amd/stoneyridge/acpi/mmio.asl
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl
index 47d5992272..6e67f5a3fa 100644
--- a/src/soc/amd/stoneyridge/acpi/soc.asl
+++ b/src/soc/amd/stoneyridge/acpi/soc.asl
@@ -15,8 +15,8 @@ Scope(PCI0) {
 /* Describe PCI INT[A-H] for the Southbridge */
 #include "pci_int.asl"
 
-/* Describe the devices in the Southbridge */
-#include "sb_fch.asl"
+/* Describe the MMIO devices in the FCH */
+#include "mmio.asl"
 
 /* Add GPIO library */
 #include <soc/amd/common/acpi/gpio_bank_lib.asl>