soc/intel/alderlake/ramstage: Fix compilation issue

Refer to
commit 0359d9d (soc/intel: Make use of PMC low power program
from common block)
commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common
code)
commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code)
commit 8971ccd (soc/intel: Move pch_misc_init() to common code)
for details

Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/alderlake/espi.c

@@ -59,7 +59,7 @@ void lpc_soc_init(struct device *dev)
 {
 	/* Legacy initialization */
 	isa_dma_init();
-	lpc_pch_misc_init();
+	pch_misc_init();
 
 	/* Enable CLKRUN_EN for power gating ESPI */
 	lpc_enable_pci_clk_cntl();
@@ -71,8 +71,8 @@ void lpc_soc_init(struct device *dev)
 		lpc_set_serirq_mode(SERIRQ_QUIET);
 
 	/* Interrupt configuration */
-	lpc_pch_enable_ioapic();
-	lpc_pch_pirq_init();
+	pch_enable_ioapic();
+	pch_pirq_init();
 	setup_i8259();
 	i8259_configure_irq_trigger(9, 1);
 }

src/soc/intel/alderlake/include/soc/pmc.h

@@ -125,6 +125,7 @@ enum pch_pmc_xtal {
 enum pch_pmc_xtal pmc_get_xtal_freq(void);
 
 #define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define  ACPI_TIM_DIS			(1 << 1)
 #define GPIO_GPE_CFG			0x1920
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))