baytrail: make default GPIO configs closer to power-on defaults
- Set config0 defaults for hysteresis disable, pad bypass, etc. - Set config1 power-on defaults. - Set pad_val for input as default. BUG=chrome-os-partner:22863 TEST=Manual. Enable GPIO_DEBUG and verify pad registers are set according to expectation. Also verify bayleybay still boots to payload loading. Change-Id: I0f1c9e4d4f39c5c56d7e14a82eb4825612e19420 Reviewed-on: https://chromium-review.googlesource.com/171903 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4866 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Shawn Nematbakhsh
Aaron Durbin
parent
5a5c886b8d
commit
0b132c3ae3
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@ -27,9 +27,9 @@
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/* #define GPIO_DEBUG */
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/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */
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#define GPSCORE_PAD_BASE IO_BASE_ADDRESS + 0x0000
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#define GPNCORE_PAD_BASE IO_BASE_ADDRESS + 0x1000
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#define GPSSUS_PAD_BASE IO_BASE_ADDRESS + 0x2000
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#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + 0x0000)
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#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + 0x1000)
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#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + 0x2000)
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/* Pad register offset */
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#define PAD_CONF0_REG 0x0
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@ -37,8 +37,8 @@
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#define PAD_VAL_REG 0x8
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/* Legacy IO register base */
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#define GPSCORE_LEGACY_BASE GPIO_BASE_ADDRESS + 0x00
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#define GPSSUS_LEGACY_BASE GPIO_BASE_ADDRESS + 0x80
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#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00)
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#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80)
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/* Some banks have no legacy GPIO interface */
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#define GP_LEGACY_BASE_NONE 0xFFFF
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@ -71,19 +71,45 @@
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#define GPIO_NEDGE_DISABLE 0
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#define GPIO_NEDGE_ENABLE 1
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/* PAD_CONF0 settings */
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#define PAD_IRQ_EN (1 << 27)
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#define PAD_LEVEL_IRQ (1 << 24)
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/* config0[29] - Disable second mask */
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#define PAD_MASK2_DISABLE (1 << 29)
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/* config0[27] - Direct Irq En */
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#define PAD_IRQ_EN (1 << 27)
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/* config0[24] - Gd Level */
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#define PAD_LEVEL_IRQ (1 << 24)
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#define PAD_EDGE_IRQ (0 << 24)
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/* config0[17] - Slow clkgate / glitch filter */
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#define PAD_SLOWGF_ENABLE (1 << 17)
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/* config0[16] - Fast clkgate / glitch filter */
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#define PAD_FASTGF_ENABLE (1 << 16)
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/* config0[15] - Hysteresis enable (inverted) */
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#define PAD_HYST_DISABLE (1 << 15)
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#define PAD_HYST_ENABLE (0 << 15)
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/* config0[14:13] - Hysteresis control */
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#define PAD_HYST_CTRL_DEFAULT (2 << 13)
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/* config0[11] - Bypass Flop */
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#define PAD_FLOP_BYPASS (1 << 11)
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#define PAD_FLOP_ENABLE (0 << 11)
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/* config0[10:9] - Pull str */
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#define PAD_PU_2K (0 << 9)
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#define PAD_PU_10K (1 << 9)
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#define PAD_PU_20K (2 << 9)
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#define PAD_PU_40K (3 << 9)
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/* config0[8:7] - Pull assign */
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#define PAD_PU_DISABLE (0 << 7)
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#define PAD_PU_UP (1 << 7)
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#define PAD_PU_DOWN (2 << 7)
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/* config0[2:0] - Func. pin mux */
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#define PAD_FUNC0 0x0
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#define PAD_FUNC1 0x1
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#define PAD_FUNC2 0x2
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@ -92,68 +118,101 @@
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#define PAD_FUNC5 0x5
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#define PAD_FUNC6 0x6
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/* PAD_VAL settings */
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#define PAD_INPUT_ENABLE (1 << 2)
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#define PAD_OUTPUT_ENABLE (1 << 1)
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/* pad config0 power-on values - We will not often want to change these */
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#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \
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PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \
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PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS)
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/* End marker */
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#define GPIO_LIST_END 0xffffffff
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/* pad config1 reg power-on values - Shouldn't need to change this */
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#define PAD_CONFIG1_DEFAULT 0x8000
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/* pad_val[2] - Iinenb - active low */
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#define PAD_VAL_INPUT_DISABLE (1 << 2)
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#define PAD_VAL_INPUT_ENABLE (0 << 2)
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/* pad_val[1] - Ioutenb - active low */
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#define PAD_VAL_OUTPUT_DISABLE (1 << 1)
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#define PAD_VAL_OUTPUT_ENABLE (0 << 1)
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/* pad_val reg power-on default varies by pad, and apparently can cause issues
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* if not set correctly, even if the pin isn't configured as GPIO. */
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#define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE)
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#define GPIO_INPUT_PU_10K \
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{ .pad_conf0 = PAD_PU_10K | PAD_PU_UP, \
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.pad_val = PAD_INPUT_ENABLE, \
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{ .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_INPUT_ENABLE, \
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.use_sel = GPIO_USE_LEGACY, \
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.io_sel = GPIO_DIR_INPUT }
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#define GPIO_OUT_LOW \
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{ .pad_conf0 = PAD_PU_DISABLE, \
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.pad_val = PAD_OUTPUT_ENABLE, \
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{ .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_OUTPUT_ENABLE, \
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.use_sel = GPIO_USE_LEGACY, \
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.io_sel = GPIO_DIR_OUTPUT, \
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.gp_lvl = GPIO_LEVEL_LOW }
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#define GPIO_OUT_HIGH \
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{ .pad_conf0 = PAD_PU_DISABLE, \
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.pad_val = PAD_OUTPUT_ENABLE, \
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{ .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_OUTPUT_ENABLE, \
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.use_sel = GPIO_USE_LEGACY, \
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.io_sel = GPIO_DIR_OUTPUT, \
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.gp_lvl = GPIO_LEVEL_HIGH }
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#define GPIO_FUNC0 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC0 }
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.pad_conf0 = PAD_FUNC0 | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_DEFAULT }
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#define GPIO_FUNC1 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC1 }
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.pad_conf0 = PAD_FUNC1 | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_DEFAULT }
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#define GPIO_FUNC2 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC2 }
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.pad_conf0 = PAD_FUNC2 | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_DEFAULT }
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#define GPIO_FUNC3 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC3 }
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.pad_conf0 = PAD_FUNC3 | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_DEFAULT }
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#define GPIO_FUNC4 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC4 }
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.pad_conf0 = PAD_FUNC4 | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_DEFAULT }
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#define GPIO_FUNC5 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC5 }
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.pad_conf0 = PAD_FUNC5 | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_DEFAULT }
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#define GPIO_FUNC6 \
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{ .use_sel = GPIO_USE_PAD, \
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.pad_conf0 = PAD_FUNC6 }
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.pad_conf0 = PAD_FUNC6 | PAD_CONFIG0_DEFAULT, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_DEFAULT }
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/* End marker */
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#define GPIO_LIST_END 0xffffffff
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#define GPIO_END \
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{ .pad_conf0 = GPIO_LIST_END }
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/* Common default GPIO settings */
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#define GPIO_INPUT GPIO_INPUT_PU_10K
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#define GPIO_UNUSED GPIO_INPUT_PU_10K
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#define GPIO_DEFAULT GPIO_FUNC0
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#define GPIO_INPUT GPIO_INPUT_PU_10K
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#define GPIO_UNUSED GPIO_INPUT_PU_10K
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#define GPIO_DEFAULT GPIO_FUNC0
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struct soc_gpio_map {
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u32 pad_conf0;
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