Initial support for Intel XE7501DEVKIT.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Steven J. Magnani
parent
ffc83041b7
commit
0b1a5a4a92
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##################################################################
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## BEGIN BOILERPLATE - DO NOT EDIT
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus payload) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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# The normal image goes at the beginning of the LinuxBIOS ROM region
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# and uses all the remaining space
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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default XIP_ROM_SIZE = 65536
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default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )
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## END BOILERPLATE
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##################################################################
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if HAVE_ACPI_TABLES object acpi_tables.o end
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object reset.o
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# Include the VGA option ROM, but only if we're compiled to use it
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if CONFIG_PCI_ROM_RUN
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if CONFIG_CONSOLE_VGA
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object vgarom.S
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else
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object no_vgarom.S
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end
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else
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object no_vgarom.S
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end
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if HAVE_FALLBACK_BOOT
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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if CONFIG_CHIP_NAME
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config chip.h
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end
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# based on sample config for tyan/s2735
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chip northbridge/intel/e7501
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device pci_domain 0 on
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device pci 0.0 on end # Chipset host controller
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device pci 0.1 on end # Host RASUM controller
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device pci 2.0 on # Hub interface B
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chip southbridge/intel/i82870 # P64H2
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device pci 1c.0 on end # IOAPIC - bus B
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device pci 1d.0 on end # Hub to PCI-B bridge
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device pci 1e.0 on end # IOAPIC - bus A
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device pci 1f.0 on end # Hub to PCI-A bridge
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end
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end
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device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
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device pci 4.0 on # Hub interface D
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chip southbridge/intel/i82870 # P64H2
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device pci 1c.0 on end # IOAPIC - bus B
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device pci 1d.0 on end # Hub to PCI-B bridge
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device pci 1e.0 on end # IOAPIC - bus A
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device pci 1f.0 on end # Hub to PCI-A bridge
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end
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end
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device pci 6.0 on end # E7501 Power management registers? (undocumented)
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chip southbridge/intel/i82801ca
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device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
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device pci 1d.1 off end # USB (not populated)
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device pci 1d.2 off end # USB (not populated)
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device pci 1e.0 on # Hub to PCI bridge
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chip drivers/pci/onboard # VGA ROM
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device pci 0.0 on end
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register "rom_address" = "_vgarom_start"
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end
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end
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device pci 1f.0 on # LPC bridge
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chip superio/smsc/lpc47b272
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.3 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.7 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # Keyboard interrupt
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irq 0x72 = 12 # Mouse interrupt
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end
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device pnp 2e.a off end # ACPI
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end
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end
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device pci 1f.1 on end # IDE
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # AC97 Audio
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device pci 1f.6 off end # AC97 Modem
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end # SB
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end # PCI_DOMAIN
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604_533Mhz
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604_533Mhz
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device apic 6 on end
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end
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end
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end
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@ -0,0 +1,234 @@
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uses HAVE_MP_TABLE
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uses HAVE_ACPI_TABLES
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uses HAVE_PIRQ_TABLE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_OPTION_TABLE
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uses IRQ_SLOT_COUNT
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uses CONFIG_MAX_CPUS
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_MAX_PHYSICAL_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses CONFIG_ROM_STREAM
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses _RAMBASE
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses HAVE_INIT_TIMER
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uses CONFIG_GDB_STUB
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses CONFIG_CHIP_NAME
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses DEBUG
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uses CPU_OPT
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uses CONFIG_IDE
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## The default definitions are used for these
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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## These are defined in target Config.lb, don't add here
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uses USE_FALLBACK_IMAGE
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uses ROM_SIZE
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uses ROM_IMAGE_SIZE
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uses FALLBACK_SIZE
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uses LINUXBIOS_EXTRA_VERSION
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## These are defined in mainboard Config.lb, don't add here
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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###
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### Build options
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###
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##
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## Build code for the fallback boot?
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##
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default HAVE_FALLBACK_BOOT=0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=12
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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## Build code to export ACPI tables?
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default HAVE_ACPI_TABLES=1
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##
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## Build code to export a CMOS option table?
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##
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default HAVE_OPTION_TABLE=0
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## CMOS checksum definitions (units == bytes)
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## These must match the checksum record in cmos.layout
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default LB_CKS_RANGE_START=128
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default LB_CKS_RANGE_END=130
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default LB_CKS_LOC=131
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
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## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=2
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default CONFIG_LOGICAL_CPUS=0
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default CONFIG_MAX_PHYSICAL_CPUS=2
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# VGA Console
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# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
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# to VGA.rom
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default CONFIG_CONSOLE_VGA=0
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default CONFIG_PCI_ROM_RUN=0
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Motherboard identification
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##
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default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
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default MAINBOARD_VENDOR="Intel"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
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default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
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###
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### LinuxBIOS layout values
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###
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## CMOS settings not currently supported due to conflicts with factory BIOS
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##
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default USE_OPTION_TABLE = 0
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##
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## LinuxBIOS C code runs at this location in RAM
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##
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default _RAMBASE=0x00004000
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##
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## Load the payload from the ROM
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##
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default CONFIG_ROM_STREAM = 1
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###
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### Defaults of options that you may want to override in the target config file
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###
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##
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## The default compiler
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##
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## Disable the gdb stub by default
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##
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default CONFIG_GDB_STUB=0
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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##
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## Select power on after power fail setting
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default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
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## Things we may not have
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default CONFIG_IDE=1
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default DEBUG=1
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default CPU_OPT="-g"
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default CONFIG_CHIP_NAME=1
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### End Options.lb
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end
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@ -0,0 +1,118 @@
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/*
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* Ported to Intel XE7501DEVKIT from Island Aruma
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* written by Stefan Reinauer <stepan@openbios.org>
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* (C) 2005 Stefan Reinauer
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* (C) 2005 Digital Design Corporation
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <assert.h>
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#include "bus.h"
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#include "ioapic.h"
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unsigned long acpi_dump_apics(unsigned long current)
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{
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unsigned int irq_start = 0;
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device_t dev = 0;
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struct resource* res = NULL;
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// SJM: Hard-code CPU LAPIC entries for now
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// Use SourcePoint numbering of processors
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
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||||
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// Southbridge IOAPIC
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||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2#2 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2#2 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
|
||||
// P64H2#1 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// P64H2#1 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
// Map ISA IRQ 0 to IRQ 2
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
|
||||
|
||||
// IRQ9 differs from ISA standard - ours is active high, level-triggered
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
|
||||
unsigned long write_acpi_tables(unsigned long start)
|
||||
{
|
||||
unsigned long current;
|
||||
acpi_rsdp_t *rsdp;
|
||||
acpi_rsdt_t *rsdt;
|
||||
acpi_madt_t *madt;
|
||||
|
||||
/* Align ACPI tables to 16byte */
|
||||
start = ( start + 0x0f ) & -0x10;
|
||||
current = start;
|
||||
|
||||
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
|
||||
|
||||
/* We need at least an RSDP and an RSDT Table */
|
||||
rsdp = (acpi_rsdp_t *) current;
|
||||
current += sizeof(acpi_rsdp_t);
|
||||
rsdt = (acpi_rsdt_t *) current;
|
||||
current += sizeof(acpi_rsdt_t);
|
||||
|
||||
/* clear all table memory */
|
||||
memset((void *)start, 0, current - start);
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt);
|
||||
acpi_write_rsdt(rsdt);
|
||||
|
||||
/*
|
||||
* We explicitly add these tables later on:
|
||||
*/
|
||||
/* QNX wants an MADT */
|
||||
printk_debug("ACPI: * MADT\n");
|
||||
|
||||
madt = (acpi_madt_t *) current;
|
||||
acpi_create_madt(madt);
|
||||
current+=madt->header.length;
|
||||
acpi_add_table(rsdt,madt);
|
||||
|
||||
printk_info("ACPI: done.\n");
|
||||
return current;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <arch/cpu.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c"
|
||||
#include "northbridge/intel/e7501/raminit.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/intel/e7501/debug.c"
|
||||
#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#define SUPERIO_PORT 0x2e
|
||||
#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
|
||||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7501/raminit.c"
|
||||
#include "northbridge/intel/e7501/reset_test.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
|
||||
// This function MUST appear last (ROMCC limitation)
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
.d0 = PCI_DEV(0, 0, 0),
|
||||
.d0f1 = PCI_DEV(0, 0, 1),
|
||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
|
||||
.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
|
||||
},
|
||||
};
|
||||
|
||||
if (bist == 0)
|
||||
{
|
||||
// Skip this if there was a built in self test failure
|
||||
|
||||
early_mtrr_init();
|
||||
enable_lapic();
|
||||
}
|
||||
|
||||
// Get the serial port running and print a welcome banner
|
||||
|
||||
lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
// Halt if there was a built in self test failure
|
||||
report_bist_failure(bist);
|
||||
|
||||
// print_pci_devices();
|
||||
|
||||
// If this is a warm boot, some initialization can be skipped
|
||||
|
||||
if (!bios_reset_detected())
|
||||
{
|
||||
enable_smbus();
|
||||
// dump_spd_registers(&memctrl[0]);
|
||||
// dump_smbus_registers();
|
||||
|
||||
// memreset_setup(); No-op for this chipset
|
||||
sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
|
||||
}
|
||||
|
||||
// NOTE: ROMCC dies with an internal compiler error
|
||||
// if the following line is removed.
|
||||
print_debug("SDRAM is up.\r\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#ifndef XE7501DEVKIT_BUS_H_INCLUDED
|
||||
#define XE7501DEVKIT_BUS_H_INCLUDED
|
||||
|
||||
// These were determined by seeing how LinuxBIOS enumerates the various
|
||||
// PCI (and PCI-like) buses on the board.
|
||||
|
||||
#define PCI_BUS_CHIPSET 0
|
||||
#define PCI_BUS_E7501_HI_B 1 // P64H2#2
|
||||
#define PCI_BUS_P64H2_2_B 2 // P64H2#2 bus B
|
||||
#define PCI_BUS_P64H2_2_A 3 // P64H2#2 bus A
|
||||
#define PCI_BUS_E7501_HI_D 4 // P64H2#1
|
||||
#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B
|
||||
#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A
|
||||
#define PCI_BUS_ICH3 7 // ICH3-S
|
||||
#define SUPERIO_BUS 8 // (arbitrary but unique bus #)
|
||||
|
||||
#endif // XE7501DEVKIT_BUS_H_INCLUDED
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
extern unsigned char _vgarom_start[];
|
||||
|
||||
extern struct chip_operations mainboard_intel_xe7501devkit_ops;
|
||||
|
||||
struct mainboard_intel_xe7501devkit_config {
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails:
|
||||
# "Error - Name is an invalid identifier in line"
|
||||
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
0 512 r 0 reserved_memory1 # We know nothing about the factory BIOS
|
||||
512 512 r 0 reserved_memory2 # More factory BIOS
|
||||
|
||||
# Work in progress.
|
||||
# This is where we would put the LB RTC_BOOT_BYTE options once the code
|
||||
# supports finding them there.
|
||||
#1024 1 e 4 boot_option
|
||||
#1025 1 e 4 last_boot
|
||||
#1026 1 e 1 ECC_memory
|
||||
#1028 4 r 0 reboot_bits
|
||||
|
||||
# Options used by XE7501DevKit
|
||||
#1032 3 e 5 baud_rate
|
||||
#1035 1 e 2 hyper_threading
|
||||
#1036 1 e 1 power_on_after_fail
|
||||
#1037 1 e 1 nmi
|
||||
|
||||
#1040 4 e 6 debug_level
|
||||
|
||||
#1048 16 h 0 check_sum
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
|
||||
checksums
|
||||
|
||||
# Checksum FROM bit-location TO bit-location STORE AT bit-location
|
||||
#checksum 1024 1047 1048
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "southbridge/intel/i82801ca/cmos_failover.c"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/intel/e7501/reset_test.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal()) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else {
|
||||
|
||||
check_cmos_failed();
|
||||
|
||||
if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
#if 0
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
#endif
|
||||
fallback_image:
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
// IOAPIC addresses determined by LinuxBIOS enumeration.
|
||||
// Someday add functions to get APIC IDs and versions from the chips themselves.
|
||||
|
||||
#define IOAPIC_ICH3 2
|
||||
#define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010
|
||||
#define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010
|
||||
#define IOAPIC_P64H2_1_BUS_B 5 // IOAPIC 5 at 04:1c.0 MBAR = fe500000 DataAddr = fe500010
|
||||
#define IOAPIC_P64H2_1_BUS_A 8 // IOAPIC 8 at 04:1e.0 MBAR = fe501000 DataAddr = fe501010
|
||||
|
||||
#define P64H2_IOAPIC_VERSION 0x20
|
||||
#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/* Run checkpir to verify any changes to this table...
|
||||
Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "bus.h"
|
||||
|
||||
#define UNUSED_INTERRUPT {0, 0}
|
||||
#define PIRQ_A 0x60
|
||||
#define PIRQ_B 0x61
|
||||
#define PIRQ_C 0x62
|
||||
#define PIRQ_D 0x63
|
||||
#define PIRQ_E 0x68
|
||||
#define PIRQ_F 0x69
|
||||
#define PIRQ_G 0x6A
|
||||
#define PIRQ_H 0x6B
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 12*sizeof(struct irq_info), // Size of this struct in bytes
|
||||
0, // PCI bus number on which the interrupt router resides
|
||||
PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router
|
||||
0, // PCI-exclusive IRQ bitmap
|
||||
PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router
|
||||
PCI_DEVICE_ID_INTEL_82801CA_LPC, // Device ID of compatible PCI interrupt router
|
||||
0, // Additional miniport information
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero
|
||||
0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)
|
||||
{
|
||||
// NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
|
||||
// This was determined from linux-2.6.11/arch/i386/pci/irq.c
|
||||
// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
|
||||
// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
|
||||
// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
|
||||
|
||||
// INTA# INTB# INTC# INTD#
|
||||
// bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
|
||||
|
||||
{PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus
|
||||
{PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1
|
||||
|
||||
// P64H2#2 Bus A
|
||||
{PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// P64H2#2 Bus B
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23)
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24)
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(3, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 25, 0}, // Slot 2C (J25)
|
||||
{PCI_BUS_P64H2_2_B, PCI_DEVFN(4, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 12, 0}, // Slot 2D (J12)
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// P64H2#1 Bus A
|
||||
{PCI_BUS_P64H2_1_A, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 20, 0}, // Slot 1A (J20)
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// P64H2#1 Bus B
|
||||
{PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet
|
||||
{PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21)
|
||||
// NOTE: Hotplug disabled on this bus
|
||||
|
||||
// ICH-3 PCI bus
|
||||
{PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video
|
||||
{PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11)
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if CONFIG_CHIP_NAME == 1
|
||||
struct chip_operations mainboard_intel_xe7501devkit_ops = {
|
||||
CHIP_NAME("Intel Xeon E7501 DevKit mainboard")
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include "bus.h"
|
||||
#include "ioapic.h"
|
||||
|
||||
// Generate MP-table IRQ numbers for PCI devices.
|
||||
#define INT_A 0
|
||||
#define INT_B 1
|
||||
#define INT_C 2
|
||||
#define INT_D 3
|
||||
#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
|
||||
|
||||
|
||||
void xe7501devkit_register_buses(struct mp_config_table *mc)
|
||||
{
|
||||
// Bus ID, Bus Type
|
||||
smp_write_bus(mc, PCI_BUS_CHIPSET, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, PCI_BUS_E7501_HI_B, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, PCI_BUS_P64H2_2_B, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, PCI_BUS_P64H2_2_A, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, PCI_BUS_E7501_HI_D, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, PCI_BUS_P64H2_1_B, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, PCI_BUS_P64H2_1_A, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, PCI_BUS_ICH3, BUSTYPE_PCI);
|
||||
smp_write_bus(mc, SUPERIO_BUS, BUSTYPE_ISA);
|
||||
}
|
||||
|
||||
void xe7501devkit_register_ioapics(struct mp_config_table *mc)
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
|
||||
// TODO: Gack. This is REALLY ugly.
|
||||
|
||||
// Southbridge IOAPIC
|
||||
smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address
|
||||
|
||||
// P64H2#2 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
|
||||
|
||||
// P64H2#2 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
|
||||
|
||||
|
||||
// P64H2#1 Bus A IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
|
||||
|
||||
// P64H2#1 Bus B IOAPIC
|
||||
dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
|
||||
if (!dev)
|
||||
BUG(); // Config.lb error?
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
|
||||
}
|
||||
|
||||
void xe7501devkit_register_interrupts(struct mp_config_table *mc)
|
||||
{
|
||||
// Chipset PCI bus
|
||||
// Type Trigger | Polarity Bus ID IRQ APIC ID PIN#
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_C), IOAPIC_ICH3, 18); // IDE
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_D), IOAPIC_ICH3, 19); // USB 1.1 Controller #2
|
||||
|
||||
// P64H2#2 Bus B
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12)
|
||||
|
||||
// P64H2#2 Bus A
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI
|
||||
|
||||
// P64H2#1 Bus B
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21)
|
||||
|
||||
// P64H2#1 Bus A
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20)
|
||||
|
||||
// ICH-3
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11)
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11)
|
||||
|
||||
// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
|
||||
|
||||
// Super I/O (ISA interrupts)
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 1, IOAPIC_ICH3, 1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 2);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 3, IOAPIC_ICH3, 3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 4, IOAPIC_ICH3, 4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 6, IOAPIC_ICH3, 6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 8, IOAPIC_ICH3, 8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 9, IOAPIC_ICH3, 9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 12, IOAPIC_ICH3, 12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 13, IOAPIC_ICH3, 13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 14, IOAPIC_ICH3, 14);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 15, IOAPIC_ICH3, 15);
|
||||
}
|
||||
|
||||
void* smp_write_config_table(void* v)
|
||||
{
|
||||
static const char sig[4] = MPC_SIGNATURE;
|
||||
static const char oem[8] = "INTEL ";
|
||||
static const char productid[12] = "XE7501DEVKIT";
|
||||
struct mp_config_table *mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
|
||||
mc->mpc_length = sizeof(*mc); // initially just the header
|
||||
mc->mpc_spec = 0x04; // Multiprocessing Spec V1.4
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
xe7501devkit_register_buses(mc);
|
||||
xe7501devkit_register_ioapics(mc);
|
||||
xe7501devkit_register_interrupts(mc);
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
|
||||
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
.section .rodata.optionrom
|
||||
.globl _vgarom_start
|
||||
_vgarom_start:
|
||||
.word 0xFFFF // Invalid option ROM signature
|
||||
.globl _vgarom_end
|
||||
_vgarom_end:
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
void hard_reset(void)
|
||||
{
|
||||
i82801ca_hard_reset();
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
.section .rodata.optionrom
|
||||
.globl _vgarom_start
|
||||
_vgarom_start:
|
||||
.incbin "../../../../../src/mainboard/intel/xe7501devkit/vga.rom"
|
||||
.globl _vgarom_end
|
||||
_vgarom_end:
|
||||
Loading…
Reference in New Issue