mainboard/google/reef: add pyro variant.
Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b Reviewed-on: https://review.coreboot.org/16855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Kevin Chiu
Aaron Durbin
parent
c3e85139e6
commit
0b1a90da76
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@ -50,14 +50,17 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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string
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default "reef" if BOARD_GOOGLE_REEF
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default "pyro" if BOARD_GOOGLE_PYRO
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config DEVICETREE
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string
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default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO
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default "variants/baseboard/devicetree.cb"
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config MAINBOARD_PART_NUMBER
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string
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default "Reef" if BOARD_GOOGLE_REEF
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default "Pyro" if BOARD_GOOGLE_PYRO
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config MAINBOARD_FAMILY
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string
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@ -67,6 +70,7 @@ config GBB_HWID
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string
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depends on CHROMEOS
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default "REEF TEST 3240" if BOARD_GOOGLE_REEF
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default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO
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config MAX_CPUS
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int
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@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF
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bool "Reef"
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select BOARD_GOOGLE_BASEBOARD_REEF
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select BASEBOARD_REEF_LAPTOP
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config BOARD_GOOGLE_PYRO
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bool "Pyro"
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select BOARD_GOOGLE_BASEBOARD_REEF
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select BASEBOARD_REEF_LAPTOP
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@ -0,0 +1 @@
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romstage-y += memory.c
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@ -0,0 +1,173 @@
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
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# Disable unused clkreq of PCIe root ports
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register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
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register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
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# GPIO for PERST_0
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# If the Board has PERST_0 signal, assign the GPIO
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# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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register "prt0_gpio" = "GPIO_PRT0_UDEF"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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# [6:0] steps of delay for SDR104/HS200, each 125ps.
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register "emmc_tx_data_cntl1" = "0x0C16"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_tx_data_cntl2" = "0x28162828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [30:24] steps of delay for SDR50, each 125ps.
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# [22:16] steps of delay for DDR50, each 125ps.
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# [14:8] steps of delay for SDR25/HS50, each 125ps.
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# [6:0] steps of delay for SDR12, each 125ps.
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register "emmc_rx_cmd_data_cntl1" = "0x00181717"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-22.3.
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# [17:16] stands for Rx Clock before Output Buffer
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
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# [6:0] steps of delay for HS200, each 125ps.
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register "emmc_rx_cmd_data_cntl2" = "0x10008"
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# Enable DPTF
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register "dptf_enable" = "1"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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register "hdaudio_pwr_gate_enable" = "1"
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register "hdaudio_bios_config_lockdown" = "1"
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# Enable lpss s0ix
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register "lpss_s0ix_enable" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route, i.e., if this route changes then the affected GPE
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# offset bits also need to be changed. This sets the PMC register
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# GPE_CFG fields.
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register "gpe0_dw1" = "PMC_GPE_N_31_0"
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register "gpe0_dw2" = "PMC_GPE_N_63_32"
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register "gpe0_dw3" = "PMC_GPE_SW_31_0"
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# Enable I2C2 bus early for TPM access
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register "i2c[2].early_init" = "1"
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# Minimum SLP S3 assertion width 28ms.
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register "slp_s3_assertion_width_usecs" = "28000"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on # - Audio
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chip drivers/generic/max98357a
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)"
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device generic 0 on end
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end
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end
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device pci 11.0 off end # - ISH
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device pci 12.0 off end # - SATA
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device pci 13.0 off end # - Root Port 2 - PCIe-A 0
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device pci 13.1 off end # - Root Port 3 - PCIe-A 1
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device pci 13.2 off end # - Root Port 4 - PCIe-A 2
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device pci 13.3 off end # - Root Port 5 - PCIe-A 3
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device pci 14.0 on
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chip drivers/intel/wifi
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register "wake" = "GPE0_DW3_00"
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device pci 00.0 on end
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end
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end # - Root Port 0 - PCIe-B 0 - Wifi
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device pci 14.1 off end # - Root Port 1 - PCIe-B 1
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device pci 15.0 on end # - XHCI
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device pci 15.1 off end # - XDCI
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device pci 16.0 on # - I2C 0
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chip drivers/i2c/da7219
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register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
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register "btn_cfg" = "50"
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register "mic_det_thr" = "500"
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register "jack_ins_deb" = "20"
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register "jack_det_rate" = ""32ms_64ms""
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register "jack_rem_deb" = "1"
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register "a_d_btn_thr" = "0xa"
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register "d_b_btn_thr" = "0x16"
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register "b_c_btn_thr" = "0x21"
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register "c_mic_btn_thr" = "0x3e"
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register "btn_avg" = "4"
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register "adc_1bit_rpt" = "1"
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register "micbias_lvl" = "2600"
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register "mic_amp_in_sel" = ""diff""
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device i2c 1a on end
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end
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end
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
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device i2c 50 on end
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end
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end # - I2C 2
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device pci 16.3 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)"
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register "probed" = "1"
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device i2c 10 on end
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end
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end # - I2C 3
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device pci 17.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
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register "wake" = "GPE0_DW1_15"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 on end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 on end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 off end # - SDIO
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device pci 1f.0 on # - LPC
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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device pci 1f.1 on end # - SMBUS
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end
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end
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@ -0,0 +1,89 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define DPTF_CPU_PASSIVE 95
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#define DPTF_CPU_CRITICAL 99
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#define DPTF_CPU_ACTIVE_AC0 90
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#define DPTF_CPU_ACTIVE_AC1 80
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#define DPTF_CPU_ACTIVE_AC2 70
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#define DPTF_CPU_ACTIVE_AC3 60
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#define DPTF_CPU_ACTIVE_AC4 50
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Battery"
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#define DPTF_TSR0_PASSIVE 48
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#define DPTF_TSR0_CRITICAL 70
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Ambient"
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#define DPTF_TSR1_PASSIVE 60
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#define DPTF_TSR1_CRITICAL 70
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Charger"
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#define DPTF_TSR2_PASSIVE 55
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#define DPTF_TSR2_CRITICAL 100
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#define DPTF_ENABLE_CHARGER
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
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Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
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Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
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Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
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Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
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})
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 0 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
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#ifdef DPTF_ENABLE_CHARGER
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/* Charger Effect on Temp Sensor 1 */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
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#endif
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/* CPU Effect on Temp Sensor 1 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 2 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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1600, /* PowerLimitMinimum */
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12000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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6000, /* PowerLimitMinimum */
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8000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <baseboard/gpio.h>
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#endif /* MAINBOARD_GPIO_H */
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@ -0,0 +1,114 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <soc/meminit.h>
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#include <variant/gpio.h>
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static const struct lpddr4_sku skus[] = {
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/*
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* K4F6E304HB-MGCJ - both logical channels While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate
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* the deneisty as 8Gb per rank.
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*/
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[0] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_8Gb_DENSITY,
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.ch1_rank_density = LP4_8Gb_DENSITY,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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.part_num = "K4F6E304HB-MGCJ",
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},
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/* K4F8E304HB-MGCJ - both logical channels */
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[1] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_8Gb_DENSITY,
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.ch1_rank_density = LP4_8Gb_DENSITY,
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.part_num = "K4F8E304HB-MGCJ",
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},
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/*
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* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
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* are listed at 16Gb there are 2 ranks per channel so indicate
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* the deneisty as 8Gb per rank.
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*/
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[2] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_8Gb_DENSITY,
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.ch1_rank_density = LP4_8Gb_DENSITY,
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.ch0_dual_rank = 1,
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.ch1_dual_rank = 1,
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.part_num = "MT53B512M32D2NP",
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.disable_periodic_retraining = 1,
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},
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/* MT53B256M32D1NP-062 WT:C - both logical channels */
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[3] = {
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.speed = LP4_SPEED_2400,
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.ch0_rank_density = LP4_8Gb_DENSITY,
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.ch1_rank_density = LP4_8Gb_DENSITY,
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.part_num = "MT53B256M32D1NP",
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.disable_periodic_retraining = 1,
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},
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/*
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||||
* H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
|
||||
* are listed at 16Gb there are 2 ranks per channel so indicate the
|
||||
* density as 8Gb per rank.
|
||||
*/
|
||||
[4] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "H9HCNNNBPUMLHR",
|
||||
},
|
||||
/* H9HCNNN8KUMLHR-NLE - both logical channels */
|
||||
[5] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.part_num = "H9HCNNN8KUMLHR",
|
||||
},
|
||||
/* Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch */
|
||||
[0xe] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 1,
|
||||
.ch1_dual_rank = 1,
|
||||
.part_num = "K4F6E304HB-MGCH",
|
||||
},
|
||||
/* Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch */
|
||||
[0xf] = {
|
||||
.speed = LP4_SPEED_2400,
|
||||
.ch0_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch1_rank_density = LP4_8Gb_DENSITY,
|
||||
.ch0_dual_rank = 0,
|
||||
.ch1_dual_rank = 0,
|
||||
.part_num = "K4F8E304HB-MGCH",
|
||||
},
|
||||
};
|
||||
|
||||
static const struct lpddr4_cfg lp4cfg = {
|
||||
.skus = skus,
|
||||
.num_skus = ARRAY_SIZE(skus),
|
||||
.swizzle_config = &baseboard_lpddr4_swizzle,
|
||||
};
|
||||
|
||||
const struct lpddr4_cfg *variant_lpddr4_config(void)
|
||||
{
|
||||
return &lp4cfg;
|
||||
}
|
||||
Loading…
Reference in New Issue