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southbrige/intel/bd82x6x: XHCI replace magic values 

Change-Id: I62674ccfb836fb0b02ac562f678cdfa44be98ae3
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9779
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Nicolas Reinecke 2015-03-29 17:51:11 +02:00 committed by Stefan Reinauer
parent 7effaa4c02
commit 0b29a7b37c
2 changed files with 6 additions and 2 deletions
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4
src/southbridge/intel/bd82x6x/pch.h
View File

@ -448,6 +448,10 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define USBOCM1 0x35a0 /* 32bit */
#define USBOCM2 0x35a4 /* 32bit */
/* XHCI USB 3.0 */
#define XUSB2PRM 0xd4 /* 32bit */
#define USB3PRM 0xdc /* 32bit */
/* ICH7 GPIOBASE */
#define GPIO_USE_SEL 0x00
#define GP_IO_SEL 0x04

4
src/southbridge/intel/bd82x6x/usb_xhci.c
View File

@ -38,8 +38,8 @@ static void usb_xhci_init(struct device *dev)
reg32 |= 1;
pci_write_config32(dev, 0x44, reg32);
pci_write_config32(dev, 0xd4, config->xhci_switchable_ports);
pci_write_config32(dev, 0xdc, config->superspeed_capable_ports);
pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports);
pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports);
/* Enable clock gating */
reg32 = pci_read_config32(dev, 0x40);